[llvm] r243192 - Fix PPCMaterializeInt to check the size of the integer based on the
Eric Christopher
echristo at gmail.com
Fri Jul 24 17:48:08 PDT 2015
Author: echristo
Date: Fri Jul 24 19:48:08 2015
New Revision: 243192
URL: http://llvm.org/viewvc/llvm-project?rev=243192&view=rev
Log:
Fix PPCMaterializeInt to check the size of the integer based on the
extension property we're requesting - zero or sign extended.
This fixes cases where we want to return a zero extended 32-bit -1
and not be sign extended for the entire register. Also updated the
already out of date comment with the current behavior.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
llvm/trunk/test/CodeGen/PowerPC/fast-isel-ret.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=243192&r1=243191&r2=243192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Fri Jul 24 19:48:08 2015
@@ -1608,17 +1608,16 @@ bool PPCFastISel::SelectRet(const Instru
if (ValLocs.size() > 1)
return false;
- // Special case for returning a constant integer of any size.
- // Materialize the constant as an i64 and copy it to the return
- // register. We still need to worry about properly extending the sign. E.g:
- // If the constant has only one bit, it means it is a boolean. Therefore
- // we can't use PPCMaterializeInt because it extends the sign which will
- // cause negations of the returned value to be incorrect as they are
- // implemented as the flip of the least significant bit.
+ // Special case for returning a constant integer of any size - materialize
+ // the constant as an i64 and copy it to the return register.
if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
CCValAssign &VA = ValLocs[0];
unsigned RetReg = VA.getLocReg();
+ // We still need to worry about properly extending the sign. For example,
+ // we could have only a single bit or a constant that needs zero
+ // extension rather than sign extension. Make sure we pass the return
+ // value extension property to integer materialization.
unsigned SrcReg =
PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() == CCValAssign::SExt);
@@ -2103,11 +2102,17 @@ unsigned PPCFastISel::PPCMaterializeInt(
&PPC::GPRCRegClass);
// If the constant is in range, use a load-immediate.
- if (isInt<16>(CI->getSExtValue())) {
+ if (UseSExt && isInt<16>(CI->getSExtValue())) {
unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
unsigned ImmReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
- .addImm( (UseSExt) ? CI->getSExtValue() : CI->getZExtValue() );
+ .addImm(CI->getSExtValue());
+ return ImmReg;
+ } else if (!UseSExt && isUInt<16>(CI->getZExtValue())) {
+ unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
+ unsigned ImmReg = createResultReg(RC);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
+ .addImm(CI->getZExtValue());
return ImmReg;
}
Modified: llvm/trunk/test/CodeGen/PowerPC/fast-isel-ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fast-isel-ret.ll?rev=243192&r1=243191&r2=243192&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fast-isel-ret.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fast-isel-ret.ll Fri Jul 24 19:48:08 2015
@@ -176,3 +176,13 @@ entry:
; ELF64: blr
ret double 2.5e-33;
}
+
+define zeroext i32 @ret19() nounwind {
+entry:
+; ELF64-LABEL: ret19
+; ELF64: li
+; ELF64: oris
+; ELF64: ori
+; ELF64: blr
+ ret i32 -1
+}
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