[llvm] r242737 - [ARM] Define subtarget feature "reserve-r9", which is used to decide
Akira Hatanaka
ahatanaka at apple.com
Mon Jul 20 16:21:30 PDT 2015
Author: ahatanak
Date: Mon Jul 20 18:21:30 2015
New Revision: 242737
URL: http://llvm.org/viewvc/llvm-project?rev=242737&view=rev
Log:
[ARM] Define subtarget feature "reserve-r9", which is used to decide
whether register r9 should be reserved.
This change is needed because we cannot use a backend option to set
cl::opt "arm-reserve-r9" when doing LTO.
Out-of-tree projects currently using cl::opt option "-arm-reserve-r9" to
reserve r9 should make changes to add subtarget feature "reserve-r9" to
the IR.
rdar://problem/21529937
Differential Revision: http://reviews.llvm.org/D11320
Modified:
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll
llvm/trunk/test/CodeGen/ARM/build-attributes.ll
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=242737&r1=242736&r2=242737&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Mon Jul 20 18:21:30 2015
@@ -154,6 +154,10 @@ def FeatureLongCalls : SubtargetFeature<
"Generate calls via indirect call "
"instructions">;
+def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
+ "Reserve R9, making it unavailable as "
+ "GPR">;
+
def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
"Don't use movt/movw pairs for 32-bit "
"imms">;
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=242737&r1=242736&r2=242737&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Jul 20 18:21:30 2015
@@ -40,10 +40,6 @@ using namespace llvm;
#include "ARMGenSubtargetInfo.inc"
static cl::opt<bool>
-ReserveR9("arm-reserve-r9", cl::Hidden,
- cl::desc("Reserve R9, making it unavailable as GPR"));
-
-static cl::opt<bool>
UseFusedMulOps("arm-use-mulops",
cl::init(true), cl::Hidden);
@@ -144,7 +140,7 @@ void ARMSubtarget::initializeEnvironment
UseSoftFloat = false;
HasThumb2 = false;
NoARM = false;
- IsR9Reserved = ReserveR9;
+ ReserveR9 = false;
NoMovt = false;
SupportsTailCall = false;
HasFP16 = false;
@@ -212,13 +208,10 @@ void ARMSubtarget::initSubtargetFeatures
if (isTargetNaCl())
stackAlignment = 16;
- if (isTargetMachO()) {
- IsR9Reserved = ReserveR9 || !HasV6Ops;
+ if (isTargetMachO())
SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
- } else {
- IsR9Reserved = ReserveR9;
+ else
SupportsTailCall = !isThumb1Only();
- }
if (Align == DefaultAlign) {
// Assume pre-ARMv6 doesn't support unaligned accesses.
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=242737&r1=242736&r2=242737&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon Jul 20 18:21:30 2015
@@ -109,8 +109,8 @@ protected:
/// NoARM - True if subtarget does not support ARM mode execution.
bool NoARM;
- /// IsR9Reserved - True if R9 is a not available as general purpose register.
- bool IsR9Reserved;
+ /// ReserveR9 - True if R9 is not available as a general purpose register.
+ bool ReserveR9;
/// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
/// 32-bit imms (including global addresses).
@@ -413,7 +413,9 @@ public:
return isThumb1Only() && isMClass();
}
- bool isR9Reserved() const { return IsR9Reserved; }
+ bool isR9Reserved() const {
+ return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
+ }
bool useMovt(const MachineFunction &MF) const;
Modified: llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll?rev=242737&r1=242736&r2=242737&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2007-03-13-InstrSched.ll Mon Jul 20 18:21:30 2015
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
; RUN: -mattr=+v6 | grep r9
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
-; RUN: -mattr=+v6 -arm-reserve-r9 -ifcvt-limit=0 -stats 2>&1 | grep asm-printer
+; RUN: -mattr=+v6,+reserve-r9 -ifcvt-limit=0 -stats 2>&1 | grep asm-printer
; | grep 35
define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) {
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=242737&r1=242736&r2=242737&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/build-attributes.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/build-attributes.ll Mon Jul 20 18:21:30 2015
@@ -122,7 +122,7 @@
; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER
; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=RELOC-OTHER
; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=PCS-R9-USE
-; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -arm-reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE
+; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE
; ARMv8.1a (AArch32)
; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
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