[llvm] r242666 - [mips] Added support for the ERETNC instruction.
Vasileios Kalintiris
Vasileios.Kalintiris at imgtec.com
Mon Jul 20 05:28:58 PDT 2015
Author: vkalintiris
Date: Mon Jul 20 07:28:56 2015
New Revision: 242666
URL: http://llvm.org/viewvc/llvm-project?rev=242666&view=rev
Log:
[mips] Added support for the ERETNC instruction.
Summary: This required adding the instruction predicate HasMips32r5.
Patch by Scott Egerton.
Reviewers: dsanders, vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11136
Added:
llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32.s
llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r2.s
llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r3.s
llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64.s
llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r2.s
llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r3.s
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Mon Jul 20 07:28:56 2015
@@ -644,16 +644,16 @@ class BRK_FM<bits<6> funct> : StdArch
// Exception return format <Cop0|1|0|funct>
//===----------------------------------------------------------------------===//
-class ER_FM<bits<6> funct> : StdArch
+class ER_FM<bits<6> funct, bit LLBit> : StdArch
{
bits<32> Inst;
let Inst{31-26} = 0x10;
let Inst{25} = 1;
- let Inst{24-6} = 0;
+ let Inst{24-7} = 0;
+ let Inst{6} = LLBit;
let Inst{5-0} = funct;
}
-
//===----------------------------------------------------------------------===//
// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Jul 20 07:28:56 2015
@@ -166,6 +166,8 @@ def HasMips32 : Predicate<"Subtarg
AssemblerPredicate<"FeatureMips32">;
def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
AssemblerPredicate<"FeatureMips32r2">;
+def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
+ AssemblerPredicate<"FeatureMips32r5">;
def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
AssemblerPredicate<"FeatureMips32r6">;
def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
@@ -242,6 +244,7 @@ class ISA_MIPS32R2 { list<Predicate> Ins
class ISA_MIPS32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
}
+class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
class ISA_MIPS64_NOT_64R6 {
list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
@@ -1290,9 +1293,10 @@ def TRAP : TrapBase<BREAK>;
def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
-def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
+def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
+def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
}
-def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
+def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
let AdditionalPredicates = [NotInMicroMips] in {
def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Mon Jul 20 07:28:56 2015
@@ -189,7 +189,7 @@ public:
}
bool hasMips32r5() const {
return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
- hasMips64r2();
+ hasMips64r5();
}
bool hasMips32r6() const {
return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt Mon Jul 20 07:28:56 2015
@@ -88,6 +88,7 @@
0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x42 0x00 0x00 0x58 # CHECK: eretnc
0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt Mon Jul 20 07:28:56 2015
@@ -126,6 +126,7 @@
0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x42 0x00 0x00 0x58 # CHECK: eretnc
# FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12
0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt Mon Jul 20 07:28:56 2015
@@ -165,6 +165,7 @@
0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x42 0x00 0x00 0x58 # CHECK: eretnc
0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt Mon Jul 20 07:28:56 2015
@@ -143,6 +143,7 @@
0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x42 0x00 0x00 0x58 # CHECK: eretnc
# FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12
0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12
Added: llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32.s?rev=242666&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32.s (added)
+++ llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32.s Mon Jul 20 07:28:56 2015
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Added: llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r2.s?rev=242666&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r2.s (added)
+++ llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r2.s Mon Jul 20 07:28:56 2015
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Added: llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r3.s?rev=242666&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r3.s (added)
+++ llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r3.s Mon Jul 20 07:28:56 2015
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Mon Jul 20 07:28:56 2015
@@ -70,6 +70,7 @@ a:
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret
+ eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
floor.w.d $f14,$f11
floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Mon Jul 20 07:28:56 2015
@@ -103,6 +103,8 @@ a:
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
+ eret
+ eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]
Added: llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64.s?rev=242666&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64.s (added)
+++ llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64.s Mon Jul 20 07:28:56 2015
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Added: llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r2.s?rev=242666&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r2.s (added)
+++ llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r2.s Mon Jul 20 07:28:56 2015
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Added: llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r3.s?rev=242666&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r3.s (added)
+++ llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r3.s Mon Jul 20 07:28:56 2015
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r3 \
+# RUN: 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Mon Jul 20 07:28:56 2015
@@ -132,6 +132,7 @@ a:
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret
+ eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
floor.l.d $f26,$f7
floor.l.s $f12,$f5
floor.w.d $f14,$f11
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=242666&r1=242665&r2=242666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Mon Jul 20 07:28:56 2015
@@ -132,6 +132,7 @@ a:
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
+ eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
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