[llvm] r241816 - AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()

[Tom Stellard]

Author: tstellar
Date: Thu Jul  9 11:30:27 2015
New Revision: 241816

URL: http://llvm.org/viewvc/llvm-project?rev=241816&view=rev
Log:
AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()

No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=241816&r1=241815&r2=241816&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Jul  9 11:30:27 2015
@@ -1625,7 +1625,10 @@ bool SIInstrInfo::isOperandLegal(const M
 
   if (MO->isReg()) {
     assert(DefinedRC);
-    const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
+    const TargetRegisterClass *RC =
+        TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
+            MRI.getRegClass(MO->getReg()) :
+            RI.getPhysRegClass(MO->getReg());
 
     // In order to be legal, the common sub-class must be equal to the
     // class of the current operand.  For example: