[llvm] r241794 - Add support for nest attribute to AArch64 backend

Hal Finkel hfinkel at anl.gov
Thu Jul 9 06:15:53 PDT 2015


----- Original Message -----
> From: "Renato Golin" <renato.golin at linaro.org>
> To: llvm-commits at cs.uiuc.edu
> Sent: Thursday, July 9, 2015 5:18:02 AM
> Subject: [llvm] r241794 - Add support for nest attribute to AArch64 backend
> 
> Author: rengolin
> Date: Thu Jul  9 05:18:02 2015
> New Revision: 241794
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=241794&view=rev
> Log:
> Add support for nest attribute to AArch64 backend
> 
> The nest attribute is currently supported on the x86 (32-bit) and
> x86-64
> backends, but not on ARM (32-bit) or AArch64. This patch adds support
> for
> nest to the AArch64 backend.
> 
> Register x18 is used by GCC for this purpose and hence is used here.
> As discussed on the GCC mailing list the register choice is an ABI
> issue
> and so choosing the same register as GCC means
> __builtin_call_with_static_chain
> is compatible.
> 
> Patch by Stephen Cross.
> 
> Modified:
>     llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td

This needs a test case.

 -Hal

> 
> Modified: llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td?rev=241794&r1=241793&r2=241794&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td
> (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td Thu Jul
>  9 05:18:02 2015
> @@ -40,6 +40,11 @@ def CC_AArch64_AAPCS : CallingConv<[
>    // slot is 64-bit.
>    CCIfByVal<CCPassByVal<8, 8>>,
>  
> +  // The 'nest' parameter, if any, is passed in X18.
> +  // Darwin uses X18 as the platform register and hence 'nest' isn't
> currently
> +  // supported there.
> +  CCIfNest<CCAssignToReg<[X18]>>,
> +
>    CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
>  
>    // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in
>    registers,
> 
> 
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-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory



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