[PATCH] D10970: [mips] Promote the result of SETCC nodes to GPR width.

[Vasileios Kalintiris]

vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: llvm-commits.

This patch modifies the existing comparison, branch, conditional-move
and select patterns, and adds new ones where needed. Also, the updated
SLT{u,i,iu} set of instructions generate a GPR width result.

The majority of the code changes in the Mips back-end fix the wrong
assumption that the result of SETCC nodes always produce an i32 value.
The changes in the common code path account for the fact that in 64-bit
MIPS targets, i1 is promoted to i32 instead of i64.

http://reviews.llvm.org/D10970

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
  lib/Target/Mips/Disassembler/MipsDisassembler.cpp
  lib/Target/Mips/MicroMipsInstrInfo.td
  lib/Target/Mips/Mips32r6InstrInfo.td
  lib/Target/Mips/Mips64InstrInfo.td
  lib/Target/Mips/Mips64r6InstrInfo.td
  lib/Target/Mips/MipsCondMov.td
  lib/Target/Mips/MipsISelLowering.cpp
  lib/Target/Mips/MipsISelLowering.h
  lib/Target/Mips/MipsInstrInfo.td
  lib/Target/Mips/MipsRegisterInfo.td
  lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  lib/Target/Mips/MipsSEISelLowering.cpp
  lib/Target/Mips/MipsSEISelLowering.h
  test/CodeGen/Mips/atomic.ll
  test/CodeGen/Mips/blez_bgez.ll
  test/CodeGen/Mips/cmov.ll
  test/CodeGen/Mips/countleading.ll
  test/CodeGen/Mips/fcmp.ll
  test/CodeGen/Mips/llvm-ir/select.ll
  test/CodeGen/Mips/octeon.ll

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