[llvm] r241404 - [X86] Fix incorrect/inefficient pushw encodings for x86-64 targets
Michael Kuperstein
michael.m.kuperstein at intel.com
Sun Jul 5 03:25:42 PDT 2015
Author: mkuper
Date: Sun Jul 5 05:25:41 2015
New Revision: 241404
URL: http://llvm.org/viewvc/llvm-project?rev=241404&view=rev
Log:
[X86] Fix incorrect/inefficient pushw encodings for x86-64 targets
Correctly support assembling "pushw $imm8" on x86-64 targets.
Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually
represent the same instruction)
This fixes PR23996
Patch by: david.l.kreitzer at intel.com
Differential Revision: http://reviews.llvm.org/D10878
Added:
llvm/trunk/test/MC/ELF/relax-arith4.s
Modified:
llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/test/MC/ELF/relax-arith.s
llvm/trunk/test/MC/ELF/relax-arith2.s
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=241404&r1=241403&r2=241404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Sun Jul 5 05:25:41 2015
@@ -220,7 +220,6 @@ static unsigned getRelaxedOpcodeArith(un
case X86::PUSH32i8: return X86::PUSHi32;
case X86::PUSH16i8: return X86::PUSHi16;
case X86::PUSH64i8: return X86::PUSH64i32;
- case X86::PUSH64i16: return X86::PUSH64i32;
}
}
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=241404&r1=241403&r2=241404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Jul 5 05:25:41 2015
@@ -1028,14 +1028,13 @@ def PUSH32rmm: I<0xFF, MRM6m, (outs), (i
IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
- "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
- Requires<[Not64BitMode]>;
+ "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
+def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
+ "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
+
def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
Requires<[Not64BitMode]>;
-def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
- "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
- Requires<[Not64BitMode]>;
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
Requires<[Not64BitMode]>;
@@ -1081,9 +1080,6 @@ let Defs = [RSP], Uses = [RSP], hasSideE
SchedRW = [WriteStore] in {
def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
"push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
-def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
- "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
- Requires<[In64BitMode]>;
def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
"push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
Requires<[In64BitMode]>;
Modified: llvm/trunk/test/MC/ELF/relax-arith.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-arith.s?rev=241404&r1=241403&r2=241404&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/relax-arith.s (original)
+++ llvm/trunk/test/MC/ELF/relax-arith.s Sun Jul 5 05:25:41 2015
@@ -115,3 +115,11 @@ bar:
cmpl $foo, bar
cmp $foo, %rbx
cmpq $foo, bar
+
+// CHECK: Disassembly of section push:
+// CHECK-NEXT: push:
+// CHECK-NEXT: 0: 66 68 00 00 pushw $0
+// CHECK-NEXT: 4: 68 00 00 00 00 pushq $0
+ .section push,"x"
+ pushw $foo
+ push $foo
Modified: llvm/trunk/test/MC/ELF/relax-arith2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-arith2.s?rev=241404&r1=241403&r2=241404&view=diff
==============================================================================
--- llvm/trunk/test/MC/ELF/relax-arith2.s (original)
+++ llvm/trunk/test/MC/ELF/relax-arith2.s Sun Jul 5 05:25:41 2015
@@ -116,3 +116,15 @@ bar:
cmpl $1, bar
cmp $-1, %rbx
cmpq $42, bar
+
+// CHECK: Disassembly of section push:
+// CHECK-NEXT: push:
+// CHECK-NEXT: 0: 66 6a 80 pushw $-128
+// CHECK-NEXT: 3: 66 6a 7f pushw $127
+// CHECK-NEXT: 6: 6a 80 pushq $-128
+// CHECK-NEXT: 8: 6a 7f pushq $127
+ .section push,"x"
+ pushw $-128
+ pushw $127
+ push $-128
+ push $127
Added: llvm/trunk/test/MC/ELF/relax-arith4.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relax-arith4.s?rev=241404&view=auto
==============================================================================
--- llvm/trunk/test/MC/ELF/relax-arith4.s (added)
+++ llvm/trunk/test/MC/ELF/relax-arith4.s Sun Jul 5 05:25:41 2015
@@ -0,0 +1,25 @@
+// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s
+
+// Test for proper instruction relaxation behavior for the push $imm
+// instruction forms. This is the 32-bit version of the push $imm tests from
+// relax-arith.s and relax-arith2.s.
+
+// CHECK: Disassembly of section push8:
+// CHECK-NEXT: push8:
+// CHECK-NEXT: 0: 66 6a 80 pushw $-128
+// CHECK-NEXT: 3: 66 6a 7f pushw $127
+// CHECK-NEXT: 6: 6a 80 pushl $-128
+// CHECK-NEXT: 8: 6a 7f pushl $127
+ .section push8,"x"
+ pushw $-128
+ pushw $127
+ push $-128
+ push $127
+
+// CHECK: Disassembly of section push32:
+// CHECK-NEXT: push32:
+// CHECK-NEXT: 0: 66 68 00 00 pushw $0
+// CHECK-NEXT: 4: 68 00 00 00 00 pushl $0
+ .section push32,"x"
+ pushw $foo
+ push $foo
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