[llvm] r241254 - Reapply r240291: Fix shl folding in DAG combiner.

[Pawel Bylica]

Author: chfast
Date: Thu Jul  2 06:44:54 2015
New Revision: 241254

URL: http://llvm.org/viewvc/llvm-project?rev=241254&view=rev
Log:
Reapply r240291: Fix shl folding in DAG combiner.

The code responsible for shl folding in the DAGCombiner was assuming incorrectly that all constants are less than 64 bits. This patch simply changes the way values are compared.

It has been reverted previously because of some problems with comparing APInt with raw uint64_t. That has been fixed/changed with r241204.

Added:
    llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=241254&r1=241253&r2=241254&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jul  2 06:44:54 2015
@@ -4278,7 +4278,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N)
   if (isNullConstant(N0))
     return N0;
   // fold (shl x, c >= size(x)) -> undef
-  if (N1C && N1C->getZExtValue() >= OpSizeInBits)
+  if (N1C && N1C->getAPIntValue().uge(OpSizeInBits))
     return DAG.getUNDEF(VT);
   // fold (shl x, 0) -> x
   if (N1C && N1C->isNullValue())

Added: llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll?rev=241254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fold-vector-shl-crash.ll Thu Jul  2 06:44:54 2015
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86    | FileCheck %s
+
+;CHECK-LABEL: test
+define <2 x i256> @test() {
+  %S = shufflevector <2 x i256> zeroinitializer, <2 x i256> <i256 -1, i256 -1>, <2 x i32> <i32 0, i32 2>
+  %B = shl <2 x i256> %S, <i256 -1, i256 -1> ; DAG Combiner crashes here
+  ret <2 x i256> %B
+}