[PATCH] [x86][AVX512] add vscalef support

[Elena Demikhovsky]

REPOSITORY
  rL LLVM

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Comment at: lib/Target/X86/X86ISelLowering.cpp:15093
@@ +15092,3 @@
+      // We specify 2 possible modes for intrinsics, with/without rounding modes.
+      // First, we check if the intrinsic may have non-default rounding mode,
+      // (IntrData->Opc1 != 0), if not, we set rounding mode to "current".
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Change comments, please

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Comment at: lib/Target/X86/X86ISelLowering.cpp:15101
@@ +15100,3 @@
+      return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
+                                  Src1, Src2, Rnd),
+                                  Mask, PassThru, Subtarget, DAG);
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braces alignment

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Comment at: lib/Target/X86/X86InstrAVX512.td:3449
@@ -3448,3 +3448,3 @@
 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
                             X86VectorVTInfo _, bit IsCommutable> {
   defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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Set IsCommutable to default 0 and do not pass zeroes.

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Comment at: lib/Target/X86/X86InstrAVX512.td:3517
@@ +3516,3 @@
+multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
+                            X86VectorVTInfo _, bit IsCommutable> {
+  defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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Why do you need IsCommutable ?

http://reviews.llvm.org/D10730

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