[PATCH] MIR Parser: verify the implicit register operands.

[Alex Lorenz]

Hi dexonsmith, bob.wilson, bogner,

This patch is based on a previous serialization patch that serializes implicit register flags (http://reviews.llvm.org/D10709).

This patch verifies that the parsed machine instructions have implicit register operands as specified by MCInstrDesc. Variadic and call instructions aren't verified.

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D10781

Files:
  lib/CodeGen/MIRParser/MIParser.cpp
  test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
  test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
  test/CodeGen/MIR/X86/expected-number-after-bb.mir
  test/CodeGen/MIR/X86/global-value-operands.mir
  test/CodeGen/MIR/X86/large-index-number-error.mir
  test/CodeGen/MIR/X86/machine-basic-block-operands.mir
  test/CodeGen/MIR/X86/machine-instructions.mir
  test/CodeGen/MIR/X86/missing-implicit-operand.mir
  test/CodeGen/MIR/X86/named-registers.mir
  test/CodeGen/MIR/X86/register-mask-operands.mir
  test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
  test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir

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