[PATCH] [mips] MFC0, MTC0 changes, COP0 register class definition.

[Daniel Sanders]

Thanks. The tests need expanding on a bit (mostly copy/paste into each ISA's test file) and the commit message needs improving (particularly the subject line) but after that it will LGTM. I'm aware you don't have commit access yet, so could you update the revision and I'll commit from there.

To elaborate on the tests that are needed: For the disassembler, the tests you've added need to be duplicated in each ISA's test (test/MC/Disassembler/Mips/$isa/valid-$isa.txt and test/MC/Disassembler/Mips/$isa/valid-$isa-el.txt for big/little endian respectively). I believe that mfc0/mtc0 also need to be included in the tests for the 64-bit ISA's since they are still valid instructions. The tests are laid out like this to make it easy to inspect the differences between the ISA's and manually check against documentation. These files should be sorted by opcode.

For the assembler, we also need to test the encoding is correct. The existing tests for this are in test/MC/Mips/*/valid.s (one for each ISA). These files are sorted alphabetically to make it easy to verify against the documentation and inspect the ISA differences using diff. Lastly, we also need to add to test/MC/Mips/$isa1/invalid-$isa2.s which tests that $isa1 rejects things that were valid for $isa2. In this case, we just need to update the existing test/MC/Mips/*/invalid-mips64.s to check that dmfc0/dmtc0 are rejected with the correct error message. If they are rejected but with the wrong error message then there are also invalid-*-xfail.txt tests that can be used.


================
Comment at: lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp:84
@@ -82,1 +83,3 @@
+      ri_cprmask[0] |= Value;
+    /* MIPS COP1 is the FPU. */
     else if (FGR32RegClass->contains(CurrentSubReg) ||
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Nit: LLVM uses '//' comments.

http://reviews.llvm.org/D10567

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