[PATCH] ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it

[John Brawn]

Looks good, but a few minor comments.


REPOSITORY
  rL LLVM

================
Comment at: lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1468
@@ +1467,3 @@
+  if (Opcode != ARM::LDRD && Opcode != ARM::STRD
+      && Opcode != ARM::t2LDRDi8 && Opcode != ARM::t2STRDi8)
+    return false;
----------------
Only LDRD is affected by the cortex-m3 erratum, so t2STRDi8 is not needed here.

================
Comment at: lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1480
@@ +1479,3 @@
+  // register when interrupted or faulted.
+  bool ShouldBreakApart = false;
+  if (EvenReg == BaseReg && STI->isCortexM3())
----------------
ShouldBreakApart isn't really the right name, as the LDRD could be converted to LDM and not broken apart.

================
Comment at: test/CodeGen/ARM/ldrd.ll:11
@@ -13,8 +10,3 @@
 
-define i64 @t(i64 %a) nounwind readonly {
-entry:
-; A8-LABEL: t:
-; A8:   ldrd r2, r3, [r2]
-
-; M3-LABEL: t:
-; M3-NOT: ldrd
+; we call the following two to force values into specific registers.
+declare i64* @get_ptr()
----------------
Capitalise the We.

http://reviews.llvm.org/D10620

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