[PATCH] MIR Serialization: Serialize register mask machine operands.

[Duncan P. N. Exon Smith]

> On 2015-Jun-23, at 16:28, Alex Lorenz <arphaman at gmail.com> wrote:
> 
> Hi dexonsmith, bob.wilson, bogner,
> 
> This patch is based on a previous serialization patch that global address machine operands (http://reviews.llvm.org/D10671).
> 
> This patch implements serialization of register mask machine operands. This patch serializes the call preserved register masks that are defined by a target, it can't serialize arbitrary register masks.
> 
> This patch also extends the TargetRegisterInfo class and TableGen so that the users of TRI can get the list of all the call preserved register masks and a list of names that correspond to each mask.
> 
> This is what the extended tablegen would produce for the X86 TRI:
> 
>  ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
>    static const uint32_t *Masks[] = {
>      CSR_32_RegMask, 
>      CSR_32EHRet_RegMask, 
>      CSR_64_RegMask, 
>      CSR_64EHRet_RegMask, 
>      CSR_64_AllRegs_RegMask, 
>      CSR_64_AllRegs_AVX_RegMask, 
>      CSR_64_Intel_OCL_BI_RegMask, 
>      CSR_64_Intel_OCL_BI_AVX_RegMask, 
>      CSR_64_Intel_OCL_BI_AVX512_RegMask, 
>      CSR_64_MostRegs_RegMask, 
>      CSR_64_RT_AllRegs_RegMask, 
>      CSR_64_RT_AllRegs_AVX_RegMask, 
>      CSR_64_RT_MostRegs_RegMask, 
>      CSR_NoRegs_RegMask, 
>      CSR_Win64_RegMask, 
>      CSR_Win64_Intel_OCL_BI_AVX_RegMask, 
>      CSR_Win64_Intel_OCL_BI_AVX512_RegMask, 
>      nullptr
>    };
>    return ArrayRef<const uint32_t *>(Masks, (size_t)17);
>  }
> 
>  ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
>    static const char *Names[] = {
>      "CSR_32",
>      "CSR_32EHRet",
>      "CSR_64",
>      "CSR_64EHRet",
>      "CSR_64_AllRegs",
>      "CSR_64_AllRegs_AVX",
>      "CSR_64_Intel_OCL_BI",
>      "CSR_64_Intel_OCL_BI_AVX",
>      "CSR_64_Intel_OCL_BI_AVX512",
>      "CSR_64_MostRegs",
>      "CSR_64_RT_AllRegs",
>      "CSR_64_RT_AllRegs_AVX",
>      "CSR_64_RT_MostRegs",
>      "CSR_NoRegs",
>      "CSR_Win64",
>      "CSR_Win64_Intel_OCL_BI_AVX",
>      "CSR_Win64_Intel_OCL_BI_AVX512",
>      nullptr
>    };
>    return ArrayRef<const char *>(Names, (size_t)17);
>  }
> 
> REPOSITORY
>  rL LLVM
> 
> http://reviews.llvm.org/D10673
> 
> Files:
>  include/llvm/Target/TargetRegisterInfo.h
>  lib/CodeGen/MIRParser/MIParser.cpp
>  lib/CodeGen/MIRPrinter.cpp
>  test/CodeGen/MIR/X86/register-mask-operands.mir
>  utils/TableGen/RegisterInfoEmitter.cpp
> 
> EMAIL PREFERENCES
>  http://reviews.llvm.org/settings/panel/emailpreferences/
> <D10673.28301.patch>

LGTM.