[PATCH] Fix instruction scheduling live register tracking

[Paweł Bylica]

Thanks Andy for your another set of comments. They helped me try another solution.

During a node unscheduling the successor with the lowest height is found and set as LiveRegGen.
The difference form previous implementation is that LiveRegGen is not updated again in consecutive unschedulings.

The implementation is quite naive and is done by doing a copy of LiveRegGens to track the initial values.
The alternative would be to nest another traversal of succesors to find the lowest one.


http://reviews.llvm.org/D9993

Files:
  lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
  test/CodeGen/X86/rrlist-livereg-corrutpion.ll

Index: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -848,17 +848,28 @@
       }
     }
 
-  for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
-       I != E; ++I) {
-    if (I->isAssignedRegDep()) {
-      if (!LiveRegDefs[I->getReg()])
+  decltype(LiveRegGens) LiveRegGensCopy;
+  for (auto &Succ : SU->Succs) {
+    if (Succ.isAssignedRegDep()) {
+      auto Reg = Succ.getReg();
+      if (!LiveRegDefs[Reg])
         ++NumLiveRegs;
       // This becomes the nearest def. Note that an earlier def may still be
       // pending if this is a two-address node.
-      LiveRegDefs[I->getReg()] = SU;
-      if (LiveRegGens[I->getReg()] == nullptr ||
-          I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
-        LiveRegGens[I->getReg()] = I->getSUnit();
+      LiveRegDefs[Reg] = SU;
+
+      // Copy LiveRegGens to keep track of initial values.
+      if (LiveRegGensCopy.empty())
+        LiveRegGensCopy = LiveRegGens;
+
+      // Update LiveRegGen only if was empty before this unscheduling.
+      // This is to avoid incorrect updating LiveRegGen set in previous run.
+      if (!LiveRegGensCopy[Reg]) {
+        // Find the successor with the lowest height.
+        if (!LiveRegGens[Reg] ||
+            Succ.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())
+          LiveRegGens[Reg] = Succ.getSUnit();
+      }      
     }
   }
   if (SU->getHeight() < MinAvailableCycle)
Index: test/CodeGen/X86/rrlist-livereg-corrutpion.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/rrlist-livereg-corrutpion.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; CHECK-LABEL: test
+define i64 @test(i64 %a, i256 %b, i1 %c) {
+  %u = zext i64 %a to i256
+  %s = add i256 %u, 1
+  %o = trunc i256 %s to i1
+  %j = add i256 %s, 1
+  %i = icmp ule i64 %a, 1
+  %f = select i1 %o, i256 undef, i256 %j
+  %d = select i1 %i, i256 %f, i256 1
+  %e = add i256 %b, 1
+  %n = select i1 %c, i256 %e, i256 %b
+  %m = trunc i256 %n to i64
+  %h = add i64 %m, 1
+  %r = zext i64 %h to i256
+  %v = lshr i256 %d, %r
+  %t = trunc i256 %v to i1
+  %q = shl i256 1, %r
+  %p = and i256 %d, %q
+  %w = icmp ule i256 %n, 1
+  %y = select i1 %t, i256 undef, i256 %p
+  %x = select i1 %w, i256 %y, i256 %d
+  %z = trunc i256 %x to i64
+  ret i64 %z
+}

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