[PATCH] [mips] [IAS] Add partial support for the ULW pseudo-instruction.

[Toma Tabacu]

================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:2389-2394
@@ +2388,8 @@
+
+    // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate()
+    // because it will make our output more similar to GAS'.
+    // NOTE: If there is no source register specified in the ULW, the parser
+    // will interpret it as $0.
+    if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
+      createAddu(ATReg, ATReg, SrcReg, Instructions);
+  }
----------------
dsanders wrote:
> Could you tell me the cases where this matters? loadImmediate() will usually emit the same thing here.
For example:
  ulw/ulhu $8, 0x8000($9)

If we give the SrcReg to loadImmediate, we generate:
  ori   $1, $9, 32768

If we do the addd locally, we generate:
  ori   $1, $zero, 32768
  addu  $1, $1, $9

GAS generates:
  addiu $1, $zero, 32768
  addu  $1, $1, $9

I added a code comment with this example to D9671.

http://reviews.llvm.org/D9663

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