[PATCH] [mips] MFC0, MTC0 changes, COP0 register class definition.
simon.dardis at imgtec.com
Fri Jun 19 07:11:32 PDT 2015
MFC0 and MTC0 were incorrectly defined as taking a pair of GP32Rs and immediate, when they take a GP32R, COP0 and an immediate.
 New register class corresponding to the registers of co-processor 0.
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