[PATCH] LLVM targeting aarch64 doesn't correctly produce aligned accesses for non-aligned data at -O0/fast-isel (-mno-unaligned-access)

[Evgeny Astigeevich]

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D10360

Files:
  llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-strict-align.ll

Index: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
@@ -1678,6 +1678,9 @@
 
 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
                                    bool WantZExt, MachineMemOperand *MMO) {
+  if(!TLI.allowsMisalignedMemoryAccesses(VT))
+    return 0;
+
   // Simplify this down to something we can handle.
   if (!simplifyAddress(Addr, VT))
     return 0;
@@ -1962,6 +1965,9 @@
 
 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
                                 MachineMemOperand *MMO) {
+  if(!TLI.allowsMisalignedMemoryAccesses(VT))
+    return false;
+
   // Simplify this down to something we can handle.
   if (!simplifyAddress(Addr, VT))
     return false;
Index: llvm/trunk/test/CodeGen/AArch64/arm64-strict-align.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-strict-align.ll
+++ llvm/trunk/test/CodeGen/AArch64/arm64-strict-align.ll
@@ -1,6 +1,7 @@
 ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-no-strict-align | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-strict-align | FileCheck %s --check-prefix=CHECK-STRICT
+; RUN: llc < %s -mtriple=arm64-apple-darwin -aarch64-strict-align -fast-isel | FileCheck %s --check-prefix=CHECK-STRICT
 
 define i32 @f0(i32* nocapture %p) nounwind {
 ; CHECK-STRICT: ldrh [[HIGH:w[0-9]+]], [x0, #2]

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