[llvm] r239659 - Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRAScheduler()
Matthias Braun
matze at braunis.de
Fri Jun 12 20:42:17 PDT 2015
Author: matze
Date: Fri Jun 12 22:42:16 2015
New Revision: 239659
URL: http://llvm.org/viewvc/llvm-project?rev=239659&view=rev
Log:
Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRAScheduler()
r213101 changed the behaviour of this method to not only affect the
PostMachineScheduler scheduler but also the PostRAScheduler scheduler,
renaming should make this fact clear. Also document that the preferred
way is to specify this in the scheduling model instead of overriding
this method.
Differential Revision: http://reviews.llvm.org/D10427
Modified:
llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.h
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Fri Jun 12 22:42:16 2015
@@ -115,12 +115,11 @@ public:
/// can be overridden.
virtual bool enableJoinGlobalCopies() const;
- /// \brief True if the subtarget should run PostMachineScheduler.
+ /// True if the subtarget should run a scheduler after register allocation.
///
- /// This only takes effect if the target has configured the
- /// PostMachineScheduler pass to run, or if the global cl::opt flag,
- /// MISchedPostRA, is set.
- virtual bool enablePostMachineScheduler() const;
+ /// By default this queries the PostRAScheduling bit in the scheduling model
+ /// which is the preferred way to influence this.
+ virtual bool enablePostRAScheduler() const;
/// \brief True if the subtarget should run the atomic expansion pass.
virtual bool enableAtomicExpand() const;
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Fri Jun 12 22:42:16 2015
@@ -347,7 +347,7 @@ bool PostMachineScheduler::runOnMachineF
if (skipOptnoneFunction(*mf.getFunction()))
return false;
- if (!mf.getSubtarget().enablePostMachineScheduler()) {
+ if (!mf.getSubtarget().enablePostRAScheduler()) {
DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
return false;
}
Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Fri Jun 12 22:42:16 2015
@@ -257,7 +257,7 @@ bool PostRAScheduler::enablePostRASchedu
TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const {
Mode = ST.getAntiDepBreakMode();
ST.getCriticalPathRCs(CriticalPathRCs);
- return ST.enablePostMachineScheduler() &&
+ return ST.enablePostRAScheduler() &&
OptLevel >= ST.getOptLevelToEnablePostRAScheduler();
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Fri Jun 12 22:42:16 2015
@@ -91,7 +91,7 @@ public:
}
const Triple &getTargetTriple() const { return TargetTriple; }
bool enableMachineScheduler() const override { return true; }
- bool enablePostMachineScheduler() const override {
+ bool enablePostRAScheduler() const override {
return isCortexA53() || isCortexA57();
}
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Fri Jun 12 22:42:16 2015
@@ -337,7 +337,7 @@ bool ARMSubtarget::hasSinCos() const {
}
// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
-bool ARMSubtarget::enablePostMachineScheduler() const {
+bool ARMSubtarget::enablePostRAScheduler() const {
return (!isThumb() || hasThumb2());
}
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Fri Jun 12 22:42:16 2015
@@ -430,7 +430,7 @@ public:
bool hasSinCos() const;
/// True for some subtargets at > -O0.
- bool enablePostMachineScheduler() const override;
+ bool enablePostRAScheduler() const override;
// enableAtomicExpand- True if we need to expand our atomics.
bool enableAtomicExpand() const override;
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Jun 12 22:42:16 2015
@@ -126,7 +126,7 @@ MipsSubtarget::MipsSubtarget(const Tripl
}
/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
-bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
+bool MipsSubtarget::enablePostRAScheduler() const { return true; }
void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
CriticalPathRCs.clear();
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Jun 12 22:42:16 2015
@@ -147,7 +147,7 @@ class MipsSubtarget : public MipsGenSubt
public:
/// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
- bool enablePostMachineScheduler() const override;
+ bool enablePostRAScheduler() const override;
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Fri Jun 12 22:42:16 2015
@@ -175,7 +175,7 @@ bool PPCSubtarget::enableMachineSchedule
}
// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
-bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
+bool PPCSubtarget::enablePostRAScheduler() const { return true; }
PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
return TargetSubtargetInfo::ANTIDEP_ALL;
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Fri Jun 12 22:42:16 2015
@@ -274,7 +274,7 @@ public:
// Scheduling customization.
bool enableMachineScheduler() const override;
// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
- bool enablePostMachineScheduler() const override;
+ bool enablePostRAScheduler() const override;
AntiDepBreakMode getAntiDepBreakMode() const override;
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
Modified: llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSubtargetInfo.cpp?rev=239659&r1=239658&r2=239659&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetSubtargetInfo.cpp Fri Jun 12 22:42:16 2015
@@ -40,7 +40,7 @@ bool TargetSubtargetInfo::enableRALocalR
return true;
}
-bool TargetSubtargetInfo::enablePostMachineScheduler() const {
+bool TargetSubtargetInfo::enablePostRAScheduler() const {
return getSchedModel().PostRAScheduler;
}
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