[PATCH] Patch to make AArch64 AsmParser be case insensitive about accepting vector register names

[Phabricator]

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D10320

Files:
  llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/trunk/test/MC/AArch64/case-insen-reg-names.s

Index: llvm/trunk/test/MC/AArch64/case-insen-reg-names.s
===================================================================
--- llvm/trunk/test/MC/AArch64/case-insen-reg-names.s
+++ llvm/trunk/test/MC/AArch64/case-insen-reg-names.s
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+
+fadd v0.2d, v5.2d, v6.2d
+fadd V0.2d, V5.2d, V6.2d
+fadd v0.2d, V5.2d, v6.2d
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]
+// CHECK: fadd v0.2d, v5.2d, v6.2d          // encoding: [0xa0,0xd4,0x66,0x4e]
Index: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1764,7 +1764,7 @@
 /// }
 
 static unsigned matchVectorRegName(StringRef Name) {
-  return StringSwitch<unsigned>(Name)
+  return StringSwitch<unsigned>(Name.lower())
       .Case("v0", AArch64::Q0)
       .Case("v1", AArch64::Q1)
       .Case("v2", AArch64::Q2)

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