[llvm] r239142 - Simplify code; NFC.
Andrea Di Biagio
Andrea_DiBiagio at sn.scee.net
Fri Jun 5 03:29:56 PDT 2015
Author: adibiagio
Date: Fri Jun 5 05:29:55 2015
New Revision: 239142
URL: http://llvm.org/viewvc/llvm-project?rev=239142&view=rev
Log:
Simplify code; NFC.
Also, moved test cases from CodeGen/X86/fold-buildvector-bug.ll into
CodeGen/X86/buildvec-insertvec.ll and regenerated CHECK lines using
update_llc_test_checks.py.
Removed:
llvm/trunk/test/CodeGen/X86/fold-buildvector-bug.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=239142&r1=239141&r2=239142&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jun 5 05:29:55 2015
@@ -619,7 +619,7 @@ static SDValue GetNegatedExpression(SDVa
// fold (fneg (fsub 0, B)) -> B
if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
- if (N0CFP->getValueAPF().isZero())
+ if (N0CFP->isZero())
return Op.getOperand(1);
// fold (fneg (fsub A, B)) -> (fsub B, A)
@@ -7864,7 +7864,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N
bool AllowNewConst = (Level < AfterLegalizeDAG);
// fold (fadd A, 0) -> A
- if (N1CFP && N1CFP->getValueAPF().isZero())
+ if (N1CFP && N1CFP->isZero())
return N0;
// fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
@@ -7995,11 +7995,11 @@ SDValue DAGCombiner::visitFSUB(SDNode *N
// If 'unsafe math' is enabled, fold lots of things.
if (Options.UnsafeFPMath) {
// (fsub A, 0) -> A
- if (N1CFP && N1CFP->getValueAPF().isZero())
+ if (N1CFP && N1CFP->isZero())
return N0;
// (fsub 0, B) -> -B
- if (N0CFP && N0CFP->getValueAPF().isZero()) {
+ if (N0CFP && N0CFP->isZero()) {
if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
return GetNegatedExpression(N1, DAG, LegalOperations);
if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
@@ -8065,7 +8065,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N
if (Options.UnsafeFPMath) {
// fold (fmul A, 0) -> 0
- if (N1CFP && N1CFP->getValueAPF().isZero())
+ if (N1CFP && N1CFP->isZero())
return N1;
// fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
@@ -12995,7 +12995,7 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNo
if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
N->getOpcode() == ISD::FDIV) {
if (isNullConstant(RHSOp) || (RHSOp.getOpcode() == ISD::ConstantFP &&
- cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
+ cast<ConstantFPSDNode>(RHSOp.getNode())->isZero()))
break;
}
@@ -13259,7 +13259,7 @@ SDValue DAGCombiner::SimplifySelectCC(SD
// Check to see if we can simplify the select into an fabs node
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
// Allow either -0.0 or 0.0
- if (CFP->getValueAPF().isZero()) {
+ if (CFP->isZero()) {
// select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
N0 == N2 && N3.getOpcode() == ISD::FNEG &&
Modified: llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll?rev=239142&r1=239141&r2=239142&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll (original)
+++ llvm/trunk/test/CodeGen/X86/buildvec-insertvec.ll Fri Jun 5 05:29:55 2015
@@ -1,15 +1,56 @@
-; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s
define void @foo(<3 x float> %in, <4 x i8>* nocapture %out) nounwind {
+; CHECK-LABEL: foo:
+; CHECK: # BB#0:
+; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
+; CHECK-NEXT: movl $255, %eax
+; CHECK-NEXT: pinsrd $3, %eax, %xmm0
+; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
+; CHECK-NEXT: movd %xmm0, (%rdi)
+; CHECK-NEXT: retq
%t0 = fptoui <3 x float> %in to <3 x i8>
%t1 = shufflevector <3 x i8> %t0, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
%t2 = insertelement <4 x i8> %t1, i8 -1, i32 3
store <4 x i8> %t2, <4 x i8>* %out, align 4
ret void
-; CHECK: foo
-; CHECK: cvttps2dq
-; CHECK-NOT: pextrd
-; CHECK: pinsrd
-; CHECK-NEXT: pshufb
-; CHECK: ret
+}
+
+; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a
+; blend with a zero vector if the build_vector contains negative zero.
+;
+; TODO: the codegen for function 'test_negative_zero_1' is sub-optimal.
+; Ideally, we should generate a single shuffle blend operation.
+
+define <4 x float> @test_negative_zero_1(<4 x float> %A) {
+; CHECK-LABEL: test_negative_zero_1:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: movapd %xmm0, %xmm1
+; CHECK-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1,0]
+; CHECK-NEXT: xorps %xmm2, %xmm2
+; CHECK-NEXT: blendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: retq
+entry:
+ %0 = extractelement <4 x float> %A, i32 0
+ %1 = insertelement <4 x float> undef, float %0, i32 0
+ %2 = insertelement <4 x float> %1, float -0.0, i32 1
+ %3 = extractelement <4 x float> %A, i32 2
+ %4 = insertelement <4 x float> %2, float %3, i32 2
+ %5 = insertelement <4 x float> %4, float 0.0, i32 3
+ ret <4 x float> %5
+}
+
+define <2 x double> @test_negative_zero_2(<2 x double> %A) {
+; CHECK-LABEL: test_negative_zero_2:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: movhpd {{.*}}(%rip), %xmm0
+; CHECK-NEXT: retq
+entry:
+ %0 = extractelement <2 x double> %A, i32 0
+ %1 = insertelement <2 x double> undef, double %0, i32 0
+ %2 = insertelement <2 x double> %1, double -0.0, i32 1
+ ret <2 x double> %2
}
Removed: llvm/trunk/test/CodeGen/X86/fold-buildvector-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-buildvector-bug.ll?rev=239141&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-buildvector-bug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fold-buildvector-bug.ll (removed)
@@ -1,40 +0,0 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s
-
-; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a
-; blend with a zero vector if the build_vector contains negative zero.
-;
-; TODO: the codegen for function 'test_negative_zero_1' is sub-optimal.
-; Ideally, we should generate a single shuffle blend operation.
-
-define <4 x float> @test_negative_zero_1(<4 x float> %A) {
-; CHECK-LABEL: test_negative_zero_1:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: movapd %xmm0, %xmm1
-; CHECK-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1,0]
-; CHECK-NEXT: xorps %xmm2, %xmm2
-; CHECK-NEXT: blendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
-; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; CHECK-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; CHECK-NEXT: retq
-entry:
- %0 = extractelement <4 x float> %A, i32 0
- %1 = insertelement <4 x float> undef, float %0, i32 0
- %2 = insertelement <4 x float> %1, float -0.0, i32 1
- %3 = extractelement <4 x float> %A, i32 2
- %4 = insertelement <4 x float> %2, float %3, i32 2
- %5 = insertelement <4 x float> %4, float 0.0, i32 3
- ret <4 x float> %5
-}
-
-define <2 x double> @test_negative_zero_2(<2 x double> %A) {
-; CHECK-LABEL: test_negative_zero_2:
-; CHECK: # BB#0: # %entry
-; CHECK-NEXT: movhpd {{.*}}(%rip), %xmm0
-; CHECK-NEXT: retq
-entry:
- %0 = extractelement <2 x double> %A, i32 0
- %1 = insertelement <2 x double> undef, double %0, i32 0
- %2 = insertelement <2 x double> %1, double -0.0, i32 1
- ret <2 x double> %2
-}
More information about the llvm-commits
mailing list