[PATCH] Implement computeKnownBits for min/max nodes

Ahmed Bougacha ahmed.bougacha at gmail.com
Thu Jun 4 11:01:39 PDT 2015


================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2435-2438
@@ -2434,1 +2434,6 @@
   }
+  case ISD::SMIN:
+  case ISD::SMAX:
+  case ISD::UMIN:
+  case ISD::UMAX: {
+    APInt Op0Zero, Op0One;
----------------
How about adding these cases to the ISD::SELECT case?  (same for sign bits).  That ought to make it obvious we're just analyzing these as SELECT variants.

http://reviews.llvm.org/D10248

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/






More information about the llvm-commits mailing list