[llvm] r238958 - R600/SI: Fix tests with triples in them
Matt Arsenault
Matthew.Arsenault at amd.com
Wed Jun 3 13:04:05 PDT 2015
Author: arsenm
Date: Wed Jun 3 15:04:05 2015
New Revision: 238958
URL: http://llvm.org/viewvc/llvm-project?rev=238958&view=rev
Log:
R600/SI: Fix tests with triples in them
Only set the triple from the command line options.
Some of these were still testing SI features and using the
old r600-- triple.
Modified:
llvm/trunk/test/CodeGen/R600/coalescer_remat.ll
llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll
llvm/trunk/test/CodeGen/R600/loop-address.ll
llvm/trunk/test/CodeGen/R600/loop-idiom.ll
llvm/trunk/test/CodeGen/R600/si-vector-hang.ll
llvm/trunk/test/CodeGen/R600/subreg-eliminate-dead.ll
llvm/trunk/test/CodeGen/R600/unroll.ll
llvm/trunk/test/CodeGen/R600/wrong-transalu-pos-fix.ll
Modified: llvm/trunk/test/CodeGen/R600/coalescer_remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/coalescer_remat.ll?rev=238958&r1=238957&r2=238958&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/coalescer_remat.ll (original)
+++ llvm/trunk/test/CodeGen/R600/coalescer_remat.ll Wed Jun 3 15:04:05 2015
@@ -1,5 +1,4 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs -o - %s | FileCheck %s
-target triple="amdgcn--"
+; RUN: llc -march=amdgcn -verify-machineinstrs -mtriple=amdgcn-- -o - %s | FileCheck %s
declare float @llvm.fma.f32(float, float, float)
Modified: llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll?rev=238958&r1=238957&r2=238958&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll (original)
+++ llvm/trunk/test/CodeGen/R600/codegen-prepare-addrmode-sext.ll Wed Jun 3 15:04:05 2015
@@ -1,12 +1,10 @@
-; RUN: opt -codegenprepare -S -o - %s | FileCheck --check-prefix=OPT %s
-; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-LLC %s
+; RUN: opt -mtriple=amdgcn-- -codegenprepare -S < %s | FileCheck -check-prefix=OPT %s
+; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI-LLC %s
-target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-target triple = "r600--"
-
-; OPT-LABEL: @test
+; OPT-LABEL: @test(
; OPT: mul nsw i32
; OPT-NEXT: sext
+
; SI-LLC-LABEL: {{^}}test:
; SI-LLC: s_mul_i32
; SI-LLC-NOT: mul
Modified: llvm/trunk/test/CodeGen/R600/loop-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/loop-address.ll?rev=238958&r1=238957&r2=238958&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/loop-address.ll (original)
+++ llvm/trunk/test/CodeGen/R600/loop-address.ll Wed Jun 3 15:04:05 2015
@@ -1,13 +1,10 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood < %s | FileCheck %s
;CHECK: ALU_PUSH
;CHECK: LOOP_START_DX10 @11
;CHECK: LOOP_BREAK @10
;CHECK: POP @10
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
-target triple = "r600--"
-
define void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) #0 {
entry:
%cmp5 = icmp sgt i32 %iterations, 0
Modified: llvm/trunk/test/CodeGen/R600/loop-idiom.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/loop-idiom.ll?rev=238958&r1=238957&r2=238958&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/loop-idiom.ll (original)
+++ llvm/trunk/test/CodeGen/R600/loop-idiom.ll Wed Jun 3 15:04:05 2015
@@ -2,10 +2,6 @@
; RUN: opt -basicaa -loop-idiom -S < %s -march=amdgcn -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
; RUN: opt -basicaa -loop-idiom -S < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
-target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-target triple = "r600--"
-
-
; Make sure loop-idiom doesn't create memcpy or memset. There are no library
; implementations of these for R600.
Modified: llvm/trunk/test/CodeGen/R600/si-vector-hang.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/si-vector-hang.ll?rev=238958&r1=238957&r2=238958&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/si-vector-hang.ll (original)
+++ llvm/trunk/test/CodeGen/R600/si-vector-hang.ll Wed Jun 3 15:04:05 2015
@@ -11,10 +11,7 @@
; CHECK: buffer_store_byte
; CHECK: buffer_store_byte
; ModuleID = 'radeon'
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
-target triple = "r600--"
-; Function Attrs: nounwind
define void @test_8_min_char(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture readonly %in0, i8 addrspace(1)* nocapture readonly %in1) #0 {
entry:
%0 = load i8, i8 addrspace(1)* %in0, align 1
Modified: llvm/trunk/test/CodeGen/R600/subreg-eliminate-dead.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/subreg-eliminate-dead.ll?rev=238958&r1=238957&r2=238958&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/subreg-eliminate-dead.ll (original)
+++ llvm/trunk/test/CodeGen/R600/subreg-eliminate-dead.ll Wed Jun 3 15:04:05 2015
@@ -1,8 +1,6 @@
-; RUN: llc -verify-machineinstrs -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck %s
; LiveRangeEdit::eliminateDeadDef did not update LiveInterval sub ranges
; properly.
-target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-target triple = "amdgcn--"
; CHECK-LABEL: foobar:
; Output with subregister liveness disabled:
Modified: llvm/trunk/test/CodeGen/R600/unroll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/unroll.ll?rev=238958&r1=238957&r2=238958&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/unroll.ll (original)
+++ llvm/trunk/test/CodeGen/R600/unroll.ll Wed Jun 3 15:04:05 2015
@@ -1,7 +1,6 @@
-; RUN: opt -loop-unroll -simplifycfg -sroa %s -S -o - | FileCheck %s
+; RUN: opt -mtriple=amdgcn-- -loop-unroll -simplifycfg -sroa %s -S -o - | FileCheck %s
+; RUN: opt -mtriple=r600-- -loop-unroll -simplifycfg -sroa %s -S -o - | FileCheck %s
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
-target triple = "r600--"
; This test contains a simple loop that initializes an array declared in
; private memory. We want to make sure these kinds of loops are always
Modified: llvm/trunk/test/CodeGen/R600/wrong-transalu-pos-fix.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/wrong-transalu-pos-fix.ll?rev=238958&r1=238957&r2=238958&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/wrong-transalu-pos-fix.ll (original)
+++ llvm/trunk/test/CodeGen/R600/wrong-transalu-pos-fix.ll Wed Jun 3 15:04:05 2015
@@ -1,14 +1,9 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc -march=r600 -mcpu=redwood -mtriple=r600-- < %s | FileCheck %s
; We want all MULLO_INT inst to be last in their instruction group
;CHECK: {{^}}fill3d:
;CHECK-NOT: MULLO_INT T[0-9]+
-; ModuleID = 'radeon'
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
-target triple = "r600--"
-
-; Function Attrs: nounwind
define void @fill3d(i32 addrspace(1)* nocapture %out) #0 {
entry:
%x.i = tail call i32 @llvm.r600.read.global.size.x() #1
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