[PATCH] Fix an assert in legalization caused by 81f64c04

[Fiona]

Hi resistor, majnemer,

81f64c04 fixed the problem of too-small shift types by promoting them during legalization, but failed to consider the case in which the shift type is too large. On an out of tree target, the shift type is i64 (because that's the pointer type, and pre-legalization, shifts are created with shift type == pointer type). But i64 isn't legal, so it tries to extend it and crashes.

This attempts to fix the problem by only performing the zext promotion if the shift-amount type is smaller than the result type; if it's both illegal and larger, we don't want to touch it at this point.

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D10128

Files:
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -604,7 +604,10 @@
 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
   SDValue Res = GetPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);
-  if (!TLI.isTypeLegal(Amt.getValueType()))
+  // Careful: we only want to extend Amt if it's illegal due to being too
+  // small, not too large.
+  if (!TLI.isTypeLegal(Amt.getValueType()) &&
+      Amt.getValueType().bitsLT(Res.getValueType()))
     Amt = ZExtPromotedInteger(N->getOperand(1));
   return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
 }
@@ -629,7 +632,8 @@
   // The input value must be properly sign extended.
   SDValue Res = SExtPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);
-  if (!TLI.isTypeLegal(Amt.getValueType()))
+  if (!TLI.isTypeLegal(Amt.getValueType()) &&
+      Amt.getValueType().bitsLT(Res.getValueType()))
     Amt = ZExtPromotedInteger(N->getOperand(1));
   return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
 }
@@ -638,7 +642,8 @@
   // The input value must be properly zero extended.
   SDValue Res = ZExtPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);
-  if (!TLI.isTypeLegal(Amt.getValueType()))
+  if (!TLI.isTypeLegal(Amt.getValueType()) &&
+      Amt.getValueType().bitsLT(Res.getValueType()))
     Amt = ZExtPromotedInteger(N->getOperand(1));
   return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
 }

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