[PATCH] Fix instruction scheduling live register tracking

PaweĊ‚ Bylica chfast at gmail.com
Fri May 29 03:25:24 PDT 2015


In http://reviews.llvm.org/D9993#180825, @atrick wrote:

> Say Rx and Ry are a physical registers and we have this DAG:
>
> - Ry = I0 Rx = I1(I0:Ry) I2(I1:Rx) I3(I1:Rx) Rx = I4(I0) I5(I4:Rx) --- We first schedule this sequence bottom-up:
>
>   Rx = I1(I0:Ry) I2(I1:Rx) I3(I1:Rx)
>
>   Giving us: Def[Rx]=null, Def[Ry]=I0 Gen[Rx]=null, Gen[Ry]=I1
>
>   Since I4 has not been scheduled, we cannot schedule I0 and need to backtrack.
>
>   Unscheduling I1, we see two successors: I2 and I3. I3 has the lower height, so we should end up with: Def[Rx]=I1, Def[Ry]=null Gen[Rx]=I3, Gen[Ry]=null
>
>   If we mistakenly picked Gen[Rx]=I2, then we would not backtrack far enough and would miscompile this example!


Agreed. But it can only happen if traversing successors in order I3, I2. Is it possible?

> So, if fixing the code to check scheduled order instead of DAG height fixes your problem, that would be the best solution.





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http://reviews.llvm.org/D9993

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