[PATCH] [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.

[Kai Nacke]

Hi dsanders,

Hi Daniel,

Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to introduce a new deconding namespace to avoid a decoding conflict.

Regards,
Kai

http://reviews.llvm.org/D10083

Files:
  lib/Target/Mips/Disassembler/MipsDisassembler.cpp
  lib/Target/Mips/Mips64InstrInfo.td
  lib/Target/Mips/MipsInstrFormats.td
  test/MC/Mips/octeon-instructions.s

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D10083.26661.patch
Type: text/x-patch
Size: 3928 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150528/13a7ed84/attachment.bin>