[polly] r238227 - Tighten the PHI modeling test cases
Tobias Grosser
tobias at grosser.es
Tue May 26 11:05:45 PDT 2015
Author: grosser
Date: Tue May 26 13:05:45 2015
New Revision: 238227
URL: http://llvm.org/viewvc/llvm-project?rev=238227&view=rev
Log:
Tighten the PHI modeling test cases
While looking through the test cases I realized we did not have a CHECK line
for a duplicate memory access which we may want to eliminate later. To ensure
we do not have (or later introduce) unnecessary memory accesses, we now tighten
the test cases to look for such a pattern (and add the CHECK: line that shows
the redundant memory access).
Modified:
polly/trunk/test/ScopInfo/phi_condition_modeling_1.ll
polly/trunk/test/ScopInfo/phi_condition_modeling_2.ll
polly/trunk/test/ScopInfo/phi_conditional_simple_1.ll
polly/trunk/test/ScopInfo/phi_loop_carried_float.ll
polly/trunk/test/ScopInfo/phi_scalar_simple_1.ll
polly/trunk/test/ScopInfo/phi_scalar_simple_2.ll
Modified: polly/trunk/test/ScopInfo/phi_condition_modeling_1.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/phi_condition_modeling_1.ll?rev=238227&r1=238226&r2=238227&view=diff
==============================================================================
--- polly/trunk/test/ScopInfo/phi_condition_modeling_1.ll (original)
+++ polly/trunk/test/ScopInfo/phi_condition_modeling_1.ll Tue May 26 13:05:45 2015
@@ -12,17 +12,24 @@
; }
;
; CHECK: Statements {
-; CHECK: Stmt_bb6
+; CHECK-LABEL: Stmt_bb6
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_bb6[i0] -> MemRef_tmp_0[] };
-; CHECK: Stmt_bb7
+; CHECK-NOT: Access
+; CHECK-LABEL: Stmt_bb7
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_bb7[i0] -> MemRef_tmp_0[] };
-; CHECK: Stmt_bb8
+; CHECK-NOT: Access
+; CHECK-LABEL: Stmt_bb8
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_bb8[i0] -> MemRef_tmp_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK: [N, c] -> { Stmt_bb8[i0] -> MemRef_A[i0] };
+; CHECK-NOT: Access
; CHECK: }
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
Modified: polly/trunk/test/ScopInfo/phi_condition_modeling_2.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/phi_condition_modeling_2.ll?rev=238227&r1=238226&r2=238227&view=diff
==============================================================================
--- polly/trunk/test/ScopInfo/phi_condition_modeling_2.ll (original)
+++ polly/trunk/test/ScopInfo/phi_condition_modeling_2.ll Tue May 26 13:05:45 2015
@@ -12,22 +12,32 @@
; }
;
; CHECK: Statements {
-; CHECK: Stmt_bb6
+; CHECK-LABEL: Stmt_bb6
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_bb6[i0] -> MemRef_tmp_0[] };
-; CHECK: Stmt_bb7
+; CHECK-NOT: Access
+; CHECK-LABEL: Stmt_bb7
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_bb7[i0] -> MemRef_tmp_0[] };
-; CHECK: Stmt_bb8
+; CHECK-NOT: Access
+; CHECK-LABEL: Stmt_bb8
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_bb8[i0] -> MemRef_tmp_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_bb8[i0] -> MemRef_tmp_0[] };
-; CHECK: Stmt_bb8b
+; CHECK-NOT: Access
+; CHECK-LABEL: Stmt_bb8b
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_bb8b[i0] -> MemRef_tmp_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK: [N, c] -> { Stmt_bb8b[i0] -> MemRef_A[i0] };
+; CHECK-NOT: Access
; CHECK: }
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
Modified: polly/trunk/test/ScopInfo/phi_conditional_simple_1.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/phi_conditional_simple_1.ll?rev=238227&r1=238226&r2=238227&view=diff
==============================================================================
--- polly/trunk/test/ScopInfo/phi_conditional_simple_1.ll (original)
+++ polly/trunk/test/ScopInfo/phi_conditional_simple_1.ll Tue May 26 13:05:45 2015
@@ -10,17 +10,24 @@
; }
;
; CHECK: Statements {
-; CHECK: Stmt_if_else
+; CHECK-LABEL: Stmt_if_else
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [c] -> { Stmt_if_else[i0] -> MemRef_phi[] };
-; CHECK: Stmt_if_then
+; CHECK-NOT: Access
+; CHECK-LABEL: Stmt_if_then
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [c] -> { Stmt_if_then[i0] -> MemRef_phi[] };
-; CHECK: Stmt_if_end
+; CHECK-NOT: Access
+; CHECK-LABEL: Stmt_if_end
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [c] -> { Stmt_if_end[i0] -> MemRef_phi[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK: [c] -> { Stmt_if_end[i0] -> MemRef_A[i0] };
+; CHECK-NOT: Access
; CHECK: }
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
Modified: polly/trunk/test/ScopInfo/phi_loop_carried_float.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/phi_loop_carried_float.ll?rev=238227&r1=238226&r2=238227&view=diff
==============================================================================
--- polly/trunk/test/ScopInfo/phi_loop_carried_float.ll (original)
+++ polly/trunk/test/ScopInfo/phi_loop_carried_float.ll Tue May 26 13:05:45 2015
@@ -7,18 +7,25 @@
; }
;
; CHECK: Statements {
-; CHECK: Stmt_bb1
+; CHECK-LABEL: Stmt_bb1
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE]
; CHECK: [N] -> { Stmt_bb1[i0] -> MemRef_tmp_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE]
; CHECK: [N] -> { Stmt_bb1[i0] -> MemRef_tmp_0[] };
-; CHECK: Stmt_bb4
+; CHECK-NOT: Access
+; CHECK-LABEL: Stmt_bb4
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE]
; CHECK: [N] -> { Stmt_bb4[i0] -> MemRef_tmp_0[] };
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE]
; CHECK: [N] -> { Stmt_bb4[i0] -> MemRef_tmp_0[] };
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE]
; CHECK: [N] -> { Stmt_bb4[i0] -> MemRef_A[i0] };
+; CHECK-NOT: Access
; CHECK: }
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
Modified: polly/trunk/test/ScopInfo/phi_scalar_simple_1.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/phi_scalar_simple_1.ll?rev=238227&r1=238226&r2=238227&view=diff
==============================================================================
--- polly/trunk/test/ScopInfo/phi_scalar_simple_1.ll (original)
+++ polly/trunk/test/ScopInfo/phi_scalar_simple_1.ll Tue May 26 13:05:45 2015
@@ -15,32 +15,42 @@ entry:
br label %for.cond
for.cond: ; preds = %for.inc4, %entry
-; CHECK: Stmt_for_cond
+; CHECK-LABEL: Stmt_for_cond
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_cond[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_cond[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
+; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK: [N] -> { Stmt_for_cond[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc4 ], [ 1, %entry ]
%x.addr.0 = phi i32 [ %x, %entry ], [ %x.addr.1.lcssa, %for.inc4 ]
%cmp = icmp slt i64 %indvars.iv, %tmp
br i1 %cmp, label %for.body, label %for.end6
for.body: ; preds = %for.cond
-; CHECK: Stmt_for_body
+; CHECK-LABEL: Stmt_for_body
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_body[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_body[i0] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
br label %for.cond1
for.cond1: ; preds = %for.inc, %for.body
-; CHECK: Stmt_for_cond1
+; CHECK-LABEL: Stmt_for_cond1
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1_lcssa[] };
+; CHECK-NOT: Access
%x.addr.1 = phi i32 [ %x.addr.0, %for.body ], [ %add, %for.inc ]
%j.0 = phi i32 [ 3, %for.body ], [ %inc, %for.inc ]
%exitcond = icmp ne i32 %j.0, %N
@@ -50,13 +60,16 @@ for.body3:
br label %for.inc
for.inc: ; preds = %for.body3
-; CHECK: Stmt_for_inc
+; CHECK-LABEL: Stmt_for_inc
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_inc[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_inc[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK: [N] -> { Stmt_for_inc[i0, i1] -> MemRef_A[1 + i0] };
+; CHECK-NOT: Access
%arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
%tmp1 = load i32, i32* %arrayidx, align 4
%add = add nsw i32 %x.addr.1, %tmp1
@@ -64,20 +77,26 @@ for.inc:
br label %for.cond1
for.end: ; preds = %for.cond1
-; CHECK: Stmt_for_end
+; CHECK-LABEL: Stmt_for_end
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_end[i0] -> MemRef_x_addr_1_lcssa[] };
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_end[i0] -> MemRef_x_addr_1_lcssa[] };
+; CHECK-NOT: Access
%x.addr.1.lcssa = phi i32 [ %x.addr.1, %for.cond1 ]
br label %for.inc4
for.inc4: ; preds = %for.end
-; CHECK: Stmt_for_inc4
+; CHECK-LABEL: Stmt_for_inc4
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_inc4[i0] -> MemRef_x_addr_1_lcssa[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_for_inc4[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
br label %for.cond
Modified: polly/trunk/test/ScopInfo/phi_scalar_simple_2.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/ScopInfo/phi_scalar_simple_2.ll?rev=238227&r1=238226&r2=238227&view=diff
==============================================================================
--- polly/trunk/test/ScopInfo/phi_scalar_simple_2.ll (original)
+++ polly/trunk/test/ScopInfo/phi_scalar_simple_2.ll Tue May 26 13:05:45 2015
@@ -17,15 +17,20 @@ entry:
br label %for.cond
for.cond: ; preds = %for.inc5, %entry
-; CHECK: Stmt_for_cond
+; CHECK-LABEL: Stmt_for_cond
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_cond[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_cond[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK: [N, c] -> { Stmt_for_cond[i0] -> MemRef_A[i0] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_cond[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc5 ], [ 0, %entry ]
%x.addr.0 = phi i32 [ %x, %entry ], [ %x.addr.1, %for.inc5 ]
%arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
@@ -34,61 +39,79 @@ for.cond:
br i1 %cmp, label %for.body, label %for.end7
for.body: ; preds = %for.cond
-; CHECK: Stmt_for_body
+; CHECK-LABEL: Stmt_for_body
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_body[i0] -> MemRef_x_addr_0[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_body[i0] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
br label %for.cond1
for.cond1: ; preds = %for.inc, %for.body
-; CHECK: Stmt_for_cond1
+; CHECK-LABEL: Stmt_for_cond1
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
%x.addr.1 = phi i32 [ %x.addr.0, %for.body ], [ %x.addr.2, %for.inc ]
%j.0 = phi i32 [ 0, %for.body ], [ %inc, %for.inc ]
%exitcond = icmp ne i32 %j.0, %N
br i1 %exitcond, label %for.body3, label %for.end
for.body3: ; preds = %for.cond1
-; CHECK: Stmt_for_body3
+; CHECK-LABEL: Stmt_for_body3
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_body3[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_body3[i0, i1] -> MemRef_x_addr_2[] };
+; CHECK-NOT: Access
%cmp4 = icmp slt i64 %indvars.iv, %tmp1
br i1 %cmp4, label %if.then, label %if.end
if.then: ; preds = %for.body3
-; CHECK: Stmt_if_then
+; CHECK-LABEL: Stmt_if_then
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_if_then[i0, i1] -> MemRef_x_addr_1[] };
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK: [N, c] -> { Stmt_if_then[i0, i1] -> MemRef_A[i0] };
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_if_then[i0, i1] -> MemRef_x_addr_2[] };
+; CHECK-NOT: Access
%arrayidx = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
%tmp2 = load i32, i32* %arrayidx, align 4
%add = add nsw i32 %x.addr.1, %tmp2
br label %if.end
if.end: ; preds = %if.then, %for.body3
-; CHECK: Stmt_if_end
+; CHECK-LABEL: Stmt_if_end
+; CHECK-NOT: Access
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_if_end[i0, i1] -> MemRef_x_addr_2[] };
+; CHECK-NOT: Access
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_if_end[i0, i1] -> MemRef_x_addr_2[] };
+; CHECK-NOT: Access
%x.addr.2 = phi i32 [ %add, %if.then ], [ %x.addr.1, %for.body3 ]
br label %for.inc
for.inc: ; preds = %if.end
-; CHECK: Stmt_for_inc
+; CHECK-LABEL: Stmt_for_inc
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_inc[i0, i1] -> MemRef_x_addr_2[] };
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
@@ -100,7 +123,7 @@ for.end:
br label %for.inc5
for.inc5: ; preds = %for.end
-; CHECK: Stmt_for_inc5
+; CHECK-LABEL: Stmt_for_inc5
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N, c] -> { Stmt_for_inc5[i0] -> MemRef_x_addr_1[] };
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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