[llvm] r237952 - [PPC64] Handle vpkudum mask pattern correctly when vpkudum isn't available

[Bill Schmidt]

Author: wschmidt
Date: Thu May 21 15:48:49 2015
New Revision: 237952

URL: http://llvm.org/viewvc/llvm-project?rev=237952&view=rev
Log:
[PPC64] Handle vpkudum mask pattern correctly when vpkudum isn't available

My recent patch to add support for ISA 2.07 vector pack/unpack
instructions didn't properly check for availability of the vpkudum
instruction when recognizing it as a special vector shuffle case.
This causes us to leave the vector shuffle in place (rather than
converting it to a vector permute) so that it can be recognized later
as a vpkudum, but that pattern is invalid for processors prior to
POWER8.  Thus LLVM crashes with an "unable to select" message.  We
observed this since one of our buildbots is configured to generate
code for a POWER7.

This patch fixes the problem by checking for availability of the
vpkudum instruction during custom lowering of vector shuffles.

I've added a test case variant for the vpkudum pattern when the
instruction isn't available.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=237952&r1=237951&r2=237952&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu May 21 15:48:49 2015
@@ -1164,13 +1164,20 @@ bool PPC::isVPKUWUMShuffleMask(ShuffleVe
 }
 
 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
-/// VPKUDUM instruction.
+/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
+/// current subtarget.
+///
 /// The ShuffleKind distinguishes between big-endian operations with
 /// two different inputs (0), either-endian operations with two identical
 /// inputs (1), and little-endian operations with two different inputs (2).
 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
                                SelectionDAG &DAG) {
+  const PPCSubtarget& Subtarget =
+    static_cast<const PPCSubtarget&>(DAG.getSubtarget());
+  if (!Subtarget.hasP8Vector())
+    return false;
+
   bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
   if (ShuffleKind == 0) {
     if (IsLE)

Modified: llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll?rev=237952&r1=237951&r2=237952&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll Thu May 21 15:48:49 2015
@@ -1,4 +1,5 @@
 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck -check-prefix=CHECK-PWR7 %s
 
 define void @VPKUDUM_unary(<2 x i64>* %A) {
 entry:
@@ -17,7 +18,12 @@ entry:
 
 ; CHECK-LABEL: @VPKUDUM_unary
 ; CHECK-NOT:   vperm
+; CHECK-NOT:   vmrglw
+; CHECK-NOT:   vmrghw
 ; CHECK:       vpkudum
+; CHECK-PWR7:  vmrglw
+; CHECK-PWR7:  vmrghw
+; CHECK-PWR7:  vmrglw
 
 define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
 entry:
@@ -40,4 +46,9 @@ entry:
 
 ; CHECK-LABEL: @VPKUDUM
 ; CHECK-NOT:   vperm
+; CHECK-NOT:   vmrglw
+; CHECK-NOT:   vmrghw
 ; CHECK:       vpkudum
+; CHECK-PWR7:  vmrglw
+; CHECK-PWR7:  vmrghw
+; CHECK-PWR7:  vmrglw