[PATCH] [X86][SSE] Improve support for 128-bit vector sign extension

[Simon Pilgrim]

REPOSITORY
  rL LLVM

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:23687
@@ -23621,1 +23686,3 @@
 
+  if (VT.isVector()) {
+    auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
----------------
delena wrote:
> I still don't understand why it should be done before type legalizer. You don't want to deal with 3 x i8 or 6 x i32.
> What information disappears after type legalizer?
What happens is that the legalizer promotes the SIGN_EXTEND nodes to a ANY_EXTEND / SIGN_EXTEND_INREG pair (see PromoteIntOp_SIGN_EXTEND) - after which its much harder to match these again for lowering ;-(

I can place the new code before the (!DCI.isBeforeLegalizeOps()) early exit but it won't hit.

http://reviews.llvm.org/D9848

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