[PATCH] [X86][SSE] Improve support for 128-bit vector sign extension

Simon Pilgrim llvm-dev at redking.me.uk
Tue May 19 01:27:07 PDT 2015


Hi qcolombet, delena, andreadb,

This patch improves support for sign extension of the lower lanes of vectors of integers by making use of the SSE41 pmovsx* sign extension instructions where possible, and optimizing the sign extension by shifts on pre-SSE41 targets (avoiding the use of i64 arithmetic shifts which require scalarization).

It converts SIGN_EXTEND nodes to SIGN_EXTEND_VECTOR_INREG where necessary, which more closely match the pmovsx* instruction than the default approach of using SIGN_EXTEND_INREG which splits the operation (into an ANY_EXTEND lowered to a shuffle followed by shifts) making instruction matching difficult during lowering. Necessary support for SIGN_EXTEND_VECTOR_INREG has been added to the DAGCombiner.

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D9848

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/pr15267.ll
  test/CodeGen/X86/vec_cast2.ll
  test/CodeGen/X86/vector-sext.ll
  test/CodeGen/X86/vselect-avx.ll

EMAIL PREFERENCES
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