[PATCH] Sparc: Implement i64 load/store support for 32-bit sparc.

[Tim Northover]

================
Comment at: lib/Target/Sparc/SparcFrameLowering.cpp:232-235
@@ -229,3 +231,6 @@
+      unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
+      MRI.replaceRegWith(preg, mapped_preg);
+    }
     // Mark the reg unused.
     MRI.setPhysRegUnused(reg);
   }
----------------
Don't you need to mark the pair unused as well? I wouldn't swear to this, but a quick look suggests that marking I0_I1 unused would implicitly mark I0 and I1 unused, but not the converse.

================
Comment at: lib/Target/Sparc/SparcFrameLowering.cpp:245
@@ +244,3 @@
+      MBB->removeLiveIn(reg);
+      MBB->addLiveIn(reg - SP::I0 + SP::O0);
+    }
----------------
Is this delta correct? I'd have expected "reg - SP::I0_I1 + SP::O0_O1" unless I'm misunderstanding the logic.

================
Comment at: lib/Target/Sparc/SparcISelLowering.cpp:2641-2642
@@ +2640,4 @@
+  EVT MemVT = LdNode->getMemoryVT();
+  if (MemVT == MVT::f128)
+    return LowerF128Load(Op, DAG);
+
----------------
I don't understand this: it's the only place a 128-bit type is mentioned at all in the patch. Why does the default action change?

================
Comment at: lib/Target/Sparc/SparcISelLowering.cpp:3313
@@ +3312,3 @@
+    //    SDValue Lo =
+    //    Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
+    SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
----------------
Commented code.

http://reviews.llvm.org/D8713

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/