[PATCH] ARM: Newer CPUs support LDRD with independent input/output regs

[Matthias Braun]

Hi t.p.northover, grosbach,

The existing code would unnecessarily break LDRD/STRD apart on
targets that support non consecutive registers for them.

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D9694

Files:
  lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  test/CodeGen/ARM/ldrd.ll

Index: lib/Target/ARM/ARMLoadStoreOptimizer.cpp
===================================================================
--- lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1590,6 +1590,11 @@
   return false;
 }
 
+/// Returns true if LDRD/STRD inputs/outputs require a register pair.
+static bool doubleMemopsNeedRegPair(const ARMSubtarget &STI) {
+  return STI.hasV7Ops() || STI.isThumb2();
+}
+
 /// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
 /// ops of the same base and incrementing offset into LDM / STM ops.
 bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
@@ -1607,7 +1612,7 @@
   RS->enterBasicBlock(&MBB);
   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
   while (MBBI != E) {
-    if (FixInvalidRegPairOp(MBB, MBBI))
+    if (!doubleMemopsNeedRegPair(*STI) && FixInvalidRegPairOp(MBB, MBBI))
       continue;
 
     bool Advance  = false;
@@ -2168,9 +2173,11 @@
           MBB->erase(Op0);
           MBB->erase(Op1);
 
-          // Add register allocation hints to form register pairs.
-          MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg);
-          MRI->setRegAllocationHint(OddReg,  ARMRI::RegPairOdd, EvenReg);
+          if (doubleMemopsNeedRegPair(*STI)) {
+            // Add register allocation hints to form register pairs.
+            MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg);
+            MRI->setRegAllocationHint(OddReg,  ARMRI::RegPairOdd, EvenReg);
+          }
         } else {
           for (unsigned i = 0; i != NumMove; ++i) {
             MachineInstr *Op = Ops.back();
Index: test/CodeGen/ARM/ldrd.ll
===================================================================
--- test/CodeGen/ARM/ldrd.ll
+++ test/CodeGen/ARM/ldrd.ll
@@ -92,6 +92,22 @@
   ret void
 }
 
+declare void @extfunc(i32, i32, i32, i32)
+
+; A8-LABEL: Func2:
+; A8: ldrd
+; A8: blx
+; A8: pop
+define void @Func2(i32* %p) {
+entry:
+  %addr0 = getelementptr i32, i32* %p, i32 0
+  %addr1 = getelementptr i32, i32* %p, i32 1
+  %v0 = load i32, i32* %addr0
+  %v1 = load i32, i32* %addr1
+  ; try to force %v0/%v1 into non-adjacent registers
+  call void @extfunc(i32 %v0, i32 0, i32 0, i32 %v1)
+  ret void
+}
 
 declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
 declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind

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