[PATCH] R600/SI: Fix bug in VGPR spilling

[Tom Stellard]

The only test case I can get for this is too big and very fragile.  The problem is that this bug fixes a spill of a VGPR96 register.  The only way to create a def of a VGPR96 register is to have an image sample instruction whose only uses in the same block are either extract_element or a machine instruction.  Compiling at -O2, the backend will select the VGPR96 image sample and then later on sink the extract elements, which gives us a VGPR96 live out that we could normally force spill by compiling with -O0.  However, at -O0 the extract elements do not get sunk, so we end up spilling 3 32-bit values instead.


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  rL LLVM

http://reviews.llvm.org/D9582

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