[llvm] r236852 - [mips][microMIPSr6] Implement ADDIUPC and LWPC instructions
Jozef Kolek
jozef.kolek at imgtec.com
Fri May 8 06:52:04 PDT 2015
Author: jkolek
Date: Fri May 8 08:52:04 2015
New Revision: 236852
URL: http://llvm.org/viewvc/llvm-project?rev=236852&view=rev
Log:
[mips][microMIPSr6] Implement ADDIUPC and LWPC instructions
This patch implements ADDIUPC and LWPC instructions using mapping.
Differential Revision: http://reviews.llvm.org/D8415
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=236852&r1=236851&r2=236852&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Fri May 8 08:52:04 2015
@@ -70,3 +70,15 @@ class ADDI_FM_MMR6<string instr_asm, bit
let Inst{20-16} = rs;
let Inst{15-0} = imm16;
}
+
+class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
+ bits<5> rt;
+ bits<19> imm;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b011110;
+ let Inst{25-21} = rt;
+ let Inst{20-19} = funct;
+ let Inst{18-0} = imm;
+}
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=236852&r1=236851&r2=236852&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Fri May 8 08:52:04 2015
@@ -19,12 +19,14 @@
class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
+class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
+class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
@@ -107,6 +109,17 @@ class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPA
list<Register> Defs = [AT];
}
+class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ Operand ImmOpnd> : MMR6Arch<instr_asm> {
+ dag OutOperandList = (outs GPROpnd:$rt);
+ dag InOperandList = (ins ImmOpnd:$imm);
+ string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
+ list<dag> Pattern = [];
+}
+
+class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
+class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
+
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@@ -117,6 +130,8 @@ let DecoderNamespace = "MicroMips32r6" i
def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
+def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
+ ISA_MICROMIPS32R6;
def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
@@ -124,6 +139,7 @@ def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MM
def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
+def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=236852&r1=236851&r2=236852&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Fri May 8 08:52:04 2015
@@ -243,7 +243,7 @@ multiclass CMP_CC_M <FIELD_CMP_FORMAT Fo
//===----------------------------------------------------------------------===//
class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd> {
+ Operand ImmOpnd> : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins ImmOpnd:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
@@ -645,7 +645,7 @@ class SDBBP_R6_DESC {
//
//===----------------------------------------------------------------------===//
-def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
+def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
@@ -694,7 +694,7 @@ def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC,
def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
def LSA_R6 : LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
-def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
+def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt?rev=236852&r1=236851&r2=236852&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt Fri May 8 08:52:04 2015
@@ -6,6 +6,8 @@
0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5
+0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100
+
# CHECK: balc 14572256
0xb4 0x37 0x96 0xb8
@@ -22,6 +24,8 @@
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
+0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
+
0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=236852&r1=236851&r2=236852&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Fri May 8 08:52:04 2015
@@ -4,12 +4,14 @@
add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10]
addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2]
addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50]
+ addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0x78,0x80,0x00,0x19]
balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8]
bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8]
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
+ lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
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