[PATCH] Sparc: Add the alternate address space load/store instructions.

[Eric Christopher]

Some inline comments. Can you elaborate on the patch description as to what you're doing and why here?

Thanks!

-eric


================
Comment at: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp:635
@@ +634,3 @@
+
+    // Possible address-space identifier after the address
+    if (getLexer().is(AsmToken::Integer)) {
----------------
Comments are complete sentences with periods.

================
Comment at: lib/Target/Sparc/Disassembler/SparcDisassembler.cpp:308
@@ -305,1 +307,3 @@
 
+  if (hasAsi) {
+    MI.addOperand(MCOperand::CreateImm(asi));
----------------
No blocks around single stmt if conditionals.

================
Comment at: lib/Target/Sparc/Disassembler/SparcDisassembler.cpp:490
@@ +489,3 @@
+
+  if (hasAsi) {
+    MI.addOperand(MCOperand::CreateImm(asi));
----------------
Ditto on the single block stmts after conditionals.

================
Comment at: lib/Target/Sparc/SparcInstr64Bit.td:488
@@ -487,3 +487,3 @@
 // ATOMICS.
-let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
-  def CASXrr: F3_1_asi<3, 0b111110, 0b10000000,
+let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
+  def CASXrr: F3_1_asi<3, 0b111110,
----------------
Can you comment on the asi magic value here and why you put it as part of the let stmt?

http://reviews.llvm.org/D8904

EMAIL PREFERENCES
  http://reviews.llvm.org/settings/panel/emailpreferences/