[llvm] r236352 - [AArch64][FastISel] Variant of the logical instructions that use two input

[Quentin Colombet]

Author: qcolombet
Date: Fri May  1 16:34:57 2015
New Revision: 236352

URL: http://llvm.org/viewvc/llvm-project?rev=236352&view=rev
Log:
[AArch64][FastISel] Variant of the logical instructions that use two input
registers cannot write on SP.

rdar://problem/20748715

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=236352&r1=236351&r2=236352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Fri May  1 16:34:57 2015
@@ -2573,7 +2573,7 @@ bool AArch64FastISel::optimizeSelect(con
     Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1);
     Src1IsKill = true;
   }
-  unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32spRegClass, Src1Reg,
+  unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
                                        Src1IsKill, Src2Reg, Src2IsKill);
   updateValueMap(SI, ResultReg);
   return true;

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll?rev=236352&r1=236351&r2=236352&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll Fri May  1 16:34:57 2015
@@ -114,3 +114,22 @@ entry:
 }
 
 declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
+
+define void @logicalReg() {
+; Make sure we generate a logical reg = reg, reg instruction without any
+; machine verifier errors.
+; CHECK-LABEL: logicalReg:
+; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: ret
+entry:
+  br i1 undef, label %cond.end, label %cond.false
+
+cond.false:
+  %cond = select i1 undef, i1 true, i1 false
+  br label %cond.end
+
+cond.end:
+  %cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
+  ret void
+}
+