[llvm] r236346 - [AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences.

[Quentin Colombet]

Author: qcolombet
Date: Fri May  1 15:57:11 2015
New Revision: 236346

URL: http://llvm.org/viewvc/llvm-project?rev=236346&view=rev
Log:
[AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences.

rdar://problem/20748715

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=236346&r1=236345&r2=236346&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Fri May  1 15:57:11 2015
@@ -3598,7 +3598,10 @@ bool AArch64FastISel::fastLowerIntrinsic
                     AArch64_AM::ASR, 31, /*WantResult=*/false);
       } else {
         assert(VT == MVT::i64 && "Unexpected value type.");
-        MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
+        // LHSReg and RHSReg cannot be killed by this Mul, since they are
+        // reused in the next instruction.
+        MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg,
+                            /*IsKill=*/false);
         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
                                         RHSReg, RHSIsKill);
         emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
@@ -3627,7 +3630,10 @@ bool AArch64FastISel::fastLowerIntrinsic
                                             AArch64::sub_32);
       } else {
         assert(VT == MVT::i64 && "Unexpected value type.");
-        MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
+        // LHSReg and RHSReg cannot be killed by this Mul, since they are
+        // reused in the next instruction.
+        MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg,
+                            /*IsKill=*/false);
         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
                                         RHSReg, RHSIsKill);
         emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll?rev=236346&r1=236345&r2=236346&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll Fri May  1 15:57:11 2015
@@ -101,3 +101,16 @@ entry:
   store i32 %cond91, i32* %addr, align 4
   ret void
 }
+
+define i64 @mul_umul(i64 %arg) {
+; CHECK-LABEL: mul_umul:
+; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
+; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
+entry:
+  %sub.ptr.div = sdiv exact i64 %arg, 8
+  %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
+  %tmp1 = extractvalue { i64, i1 } %tmp, 0
+  ret i64 %tmp1
+}
+
+declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)