[llvm] r236146 - [Sparc] Really add sparcel architecture support.
Douglas Katzman
dougk at google.com
Wed Apr 29 13:30:58 PDT 2015
Author: dougk
Date: Wed Apr 29 15:30:57 2015
New Revision: 236146
URL: http://llvm.org/viewvc/llvm-project?rev=236146&view=rev
Log:
[Sparc] Really add sparcel architecture support.
Mostly copy-and-paste from Sparc v8 architecture.
Differential Revision: http://reviews.llvm.org/D8741
Modified:
llvm/trunk/include/llvm/Object/ELFObjectFile.h
llvm/trunk/lib/MC/MCObjectFileInfo.cpp
llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
Modified: llvm/trunk/include/llvm/Object/ELFObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ELFObjectFile.h?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/ELFObjectFile.h (original)
+++ llvm/trunk/include/llvm/Object/ELFObjectFile.h Wed Apr 29 15:30:57 2015
@@ -928,7 +928,7 @@ unsigned ELFObjectFile<ELFT>::getArch()
case ELF::EM_SPARC:
case ELF::EM_SPARC32PLUS:
- return Triple::sparc;
+ return IsLittleEndian ? Triple::sparcel : Triple::sparc;
case ELF::EM_SPARCV9:
return Triple::sparcv9;
Modified: llvm/trunk/lib/MC/MCObjectFileInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectFileInfo.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCObjectFileInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCObjectFileInfo.cpp Wed Apr 29 15:30:57 2015
@@ -337,6 +337,7 @@ void MCObjectFileInfo::InitELFMCObjectFi
TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
dwarf::DW_EH_PE_udata8;
break;
+ case Triple::sparcel:
case Triple::sparc:
if (RelocM == Reloc::PIC_) {
LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
Modified: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Wed Apr 29 15:30:57 2015
@@ -907,10 +907,10 @@ bool SparcAsmParser::matchSparcAsmModifi
return true;
}
-
extern "C" void LLVMInitializeSparcAsmParser() {
RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
+ RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget);
}
#define GET_REGISTER_MATCHER
Modified: llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp Wed Apr 29 15:30:57 2015
@@ -16,6 +16,8 @@
#include "SparcSubtarget.h"
#include "llvm/MC/MCDisassembler.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
@@ -38,17 +40,15 @@ public:
raw_ostream &VStream,
raw_ostream &CStream) const override;
};
-
}
namespace llvm {
- extern Target TheSparcTarget, TheSparcV9Target;
+extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget;
}
-static MCDisassembler *createSparcDisassembler(
- const Target &T,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) {
+static MCDisassembler *createSparcDisassembler(const Target &T,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx) {
return new SparcDisassembler(STI, Ctx);
}
@@ -59,10 +59,10 @@ extern "C" void LLVMInitializeSparcDisas
createSparcDisassembler);
TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
createSparcDisassembler);
+ TargetRegistry::RegisterMCDisassembler(TheSparcelTarget,
+ createSparcDisassembler);
}
-
-
static const unsigned IntRegDecoderTable[] = {
SP::G0, SP::G1, SP::G2, SP::G3,
SP::G4, SP::G5, SP::G6, SP::G7,
@@ -208,16 +208,19 @@ static DecodeStatus DecodeSWAP(MCInst &I
/// Read four bytes from the ArrayRef and return 32 bit word.
static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
- uint64_t &Size, uint32_t &Insn) {
+ uint64_t &Size, uint32_t &Insn,
+ bool IsLittleEndian) {
// We want to read exactly 4 Bytes of data.
if (Bytes.size() < 4) {
Size = 0;
return MCDisassembler::Fail;
}
- // Encoded as a big-endian 32-bit word in the stream.
- Insn =
- (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
+ Insn = IsLittleEndian
+ ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
+ (Bytes[3] << 24)
+ : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
+ (Bytes[0] << 24);
return MCDisassembler::Success;
}
@@ -228,12 +231,12 @@ DecodeStatus SparcDisassembler::getInstr
raw_ostream &VStream,
raw_ostream &CStream) const {
uint32_t Insn;
-
- DecodeStatus Result = readInstruction32(Bytes, Address, Size, Insn);
+ bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
+ DecodeStatus Result =
+ readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;
-
// Calling the auto-generated decoder function.
Result =
decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp Wed Apr 29 15:30:57 2015
@@ -216,9 +216,9 @@ namespace {
return true;
}
- bool is64Bit() const {
- StringRef name = TheTarget.getName();
- return name == "sparcv9";
+ bool is64Bit() const { return StringRef(TheTarget.getName()) == "sparcv9"; }
+ bool isLittleEndian() const {
+ return StringRef(TheTarget.getName()) == "sparcel";
}
};
@@ -246,7 +246,7 @@ namespace {
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
- return createSparcELFObjectWriter(OS, is64Bit(), OSABI);
+ return createSparcELFObjectWriter(OS, is64Bit(), isLittleEndian(), OSABI);
}
};
Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp Wed Apr 29 15:30:57 2015
@@ -106,7 +106,9 @@ unsigned SparcELFObjectWriter::GetRelocT
}
MCObjectWriter *llvm::createSparcELFObjectWriter(raw_pwrite_stream &OS,
- bool Is64Bit, uint8_t OSABI) {
+ bool Is64Bit,
+ bool IsLittleEndian,
+ uint8_t OSABI) {
MCELFObjectTargetWriter *MOTW = new SparcELFObjectWriter(Is64Bit, OSABI);
- return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false);
+ return createELFObjectWriter(MOTW, OS, IsLittleEndian);
}
Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp Wed Apr 29 15:30:57 2015
@@ -18,12 +18,12 @@
using namespace llvm;
-void SparcELFMCAsmInfo::anchor() { }
+void SparcELFMCAsmInfo::anchor() {}
SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) {
- IsLittleEndian = false;
Triple TheTriple(TT);
bool isV9 = (TheTriple.getArch() == Triple::sparcv9);
+ IsLittleEndian = (TheTriple.getArch() == Triple::sparcel);
if (isV9) {
PointerSize = CalleeSaveStackSlotSize = 8;
Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp Wed Apr 29 15:30:57 2015
@@ -21,6 +21,7 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -78,16 +79,23 @@ MCCodeEmitter *llvm::createSparcMCCodeEm
return new SparcMCCodeEmitter(Ctx);
}
-void SparcMCCodeEmitter::
-EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+void SparcMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
- // Output the constant in big endian byte order.
- for (unsigned i = 0; i != 4; ++i) {
- OS << (char)(Bits >> 24);
- Bits <<= 8;
+ if (Ctx.getAsmInfo()->isLittleEndian()) {
+ // Output the bits in little-endian byte order.
+ for (unsigned i = 0; i != 4; ++i) {
+ OS << (char)Bits;
+ Bits >>= 8;
+ }
+ } else {
+ // Output the bits in big-endian byte order.
+ for (unsigned i = 0; i != 4; ++i) {
+ OS << (char)(Bits >> 24);
+ Bits <<= 8;
+ }
}
unsigned tlsOpNo = 0;
switch (MI.getOpcode()) {
Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Wed Apr 29 15:30:57 2015
@@ -146,8 +146,9 @@ extern "C" void LLVMInitializeSparcTarge
// Register the MC asm info.
RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo);
RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo);
+ RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo);
- for (Target *T : {&TheSparcTarget, &TheSparcV9Target}) {
+ for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) {
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo);
@@ -176,8 +177,9 @@ extern "C" void LLVMInitializeSparcTarge
// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget,
- createSparcMCCodeGenInfo);
+ createSparcMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target,
- createSparcV9MCCodeGenInfo);
-
+ createSparcV9MCCodeGenInfo);
+ TargetRegistry::RegisterMCCodeGenInfo(TheSparcelTarget,
+ createSparcMCCodeGenInfo);
}
Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h Wed Apr 29 15:30:57 2015
@@ -31,16 +31,15 @@ class raw_ostream;
extern Target TheSparcTarget;
extern Target TheSparcV9Target;
+extern Target TheSparcelTarget;
MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
-MCAsmBackend *createSparcAsmBackend(const Target &T,
- const MCRegisterInfo &MRI,
- StringRef TT,
- StringRef CPU);
+MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
+ StringRef TT, StringRef CPU);
MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
- uint8_t OSABI);
+ bool IsLIttleEndian, uint8_t OSABI);
} // End llvm namespace
// Defines symbolic names for Sparc registers. This defines a mapping from
Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Wed Apr 29 15:30:57 2015
@@ -445,4 +445,5 @@ bool SparcAsmPrinter::PrintAsmMemoryOper
extern "C" void LLVMInitializeSparcAsmPrinter() {
RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget);
RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target);
+ RegisterAsmPrinter<SparcAsmPrinter> Z(TheSparcelTarget);
}
Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Wed Apr 29 15:30:57 2015
@@ -22,11 +22,13 @@ extern "C" void LLVMInitializeSparcTarge
// Register the target.
RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
+ RegisterTargetMachine<SparcelTargetMachine> Z(TheSparcelTarget);
}
-static std::string computeDataLayout(bool is64Bit) {
- // Sparc is big endian.
- std::string Ret = "E-m:e";
+static std::string computeDataLayout(const Triple &T, bool is64Bit) {
+ // Sparc is typically big endian, but some are little.
+ std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
+ Ret += "-m:e";
// Some ABIs have 32bit pointers.
if (!is64Bit)
@@ -57,8 +59,8 @@ SparcTargetMachine::SparcTargetMachine(c
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit)
- : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
- CM, OL),
+ : LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS,
+ Options, RM, CM, OL),
TLOF(make_unique<SparcELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this, is64bit) {
initAsmInfo();
@@ -116,12 +118,18 @@ SparcV8TargetMachine::SparcV8TargetMachi
void SparcV9TargetMachine::anchor() { }
-SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
- StringRef TT, StringRef CPU,
- StringRef FS,
+SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
const TargetOptions &Options,
- Reloc::Model RM,
- CodeModel::Model CM,
+ Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
- : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
-}
+ : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+
+void SparcelTargetMachine::anchor() {}
+
+SparcelTargetMachine::SparcelTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Wed Apr 29 15:30:57 2015
@@ -58,9 +58,18 @@ public:
class SparcV9TargetMachine : public SparcTargetMachine {
virtual void anchor();
public:
- SparcV9TargetMachine(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
- const TargetOptions &Options,
+ SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU,
+ StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
+};
+
+class SparcelTargetMachine : public SparcTargetMachine {
+ virtual void anchor();
+
+public:
+ SparcelTargetMachine(const Target &T, StringRef TT, StringRef CPU,
+ StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
};
Modified: llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp?rev=236146&r1=236145&r2=236146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp Wed Apr 29 15:30:57 2015
@@ -14,10 +14,13 @@ using namespace llvm;
Target llvm::TheSparcTarget;
Target llvm::TheSparcV9Target;
+Target llvm::TheSparcelTarget;
extern "C" void LLVMInitializeSparcTargetInfo() {
- RegisterTarget<Triple::sparc, /*HasJIT=*/ true>
- X(TheSparcTarget, "sparc", "Sparc");
- RegisterTarget<Triple::sparcv9, /*HasJIT=*/ true>
- Y(TheSparcV9Target, "sparcv9", "Sparc V9");
+ RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(TheSparcTarget, "sparc",
+ "Sparc");
+ RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(TheSparcV9Target,
+ "sparcv9", "Sparc V9");
+ RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(TheSparcelTarget,
+ "sparcel", "Sparc LE");
}
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