[llvm] r235635 - [Hexagon] Fix compiler warnings in release build

[Aaron Ballman]

On Thu, Apr 23, 2015 at 4:26 PM, Krzysztof Parzyszek
<kparzysz at codeaurora.org> wrote:
> Author: kparzysz
> Date: Thu Apr 23 15:26:21 2015
> New Revision: 235635
>
> URL: http://llvm.org/viewvc/llvm-project?rev=235635&view=rev
> Log:
> [Hexagon] Fix compiler warnings in release build
>
> Patch by Aditya Nandakumar.
>
> Modified:
>     llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
>     llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp?rev=235635&r1=235634&r2=235635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp Thu Apr 23 15:26:21 2015
> @@ -170,6 +170,8 @@ static bool areCombinableOperations(cons
>                                      MachineInstr *LowRegInst) {
>    unsigned HiOpc = HighRegInst->getOpcode();
>    unsigned LoOpc = LowRegInst->getOpcode();
> +  (void)HiOpc; // Fix compiler warning
> +  (void)LoOpc; // Fix compiler warning
>    assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) &&
>           (LoOpc == Hexagon::A2_tfr || LoOpc == Hexagon::A2_tfrsi) &&
>           "Assume individual instructions are of a combinable type");
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=235635&r1=235634&r2=235635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Thu Apr 23 15:26:21 2015
> @@ -580,6 +580,7 @@ void HexagonFrameLowering::insertEpilogu
>    // Handle EH_RETURN.
>    if (RetOpc == Hexagon::EH_RETURN_JMPR) {
>      MachineOperand &OffsetReg  = RetI->getOperand(0);
> +    (void)OffsetReg; // Silence compiler warning.
>      assert(OffsetReg.isReg() && "Offset should be in register!");

Any reason not to remove OffsetReg entirely and just call
RetI->getOperand(0).isReg() in the assert?

>      BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::L2_deallocframe));
>      BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::A2_add), SP)
> @@ -818,6 +819,7 @@ void HexagonFrameLowering::eliminateCall
>        MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {
>    MachineInstr &MI = *I;
>    unsigned Opc = MI.getOpcode();
> +  (void)Opc; // Silence compiler warning.
>    assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
>           "Cannot handle this call frame pseudo instruction");
>    MBB.erase(I);
> @@ -993,7 +995,7 @@ void HexagonFrameLowering::processFuncti
>
>
>  #ifndef NDEBUG
> -void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
> +static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
>    dbgs() << '{';
>    for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
>      unsigned R = x;
> @@ -1007,6 +1009,7 @@ void dump_registers(BitVector &Regs, con
>  bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
>        const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
>    const Function &F = *MF.getFunction();
> +  (void)F; // Silence compiler warning.
>    DEBUG(dbgs() << LLVM_FUNCTION_NAME << " on " << F.getName() << '\n');

Same general concept here as above.

~Aaron

>    MachineFrameInfo *MFI = MF.getFrameInfo();
>    BitVector SRegs(Hexagon::NUM_TARGET_REGS);
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits