[PATCH] [mips] Add the SoftFloat MipsSubtarget feature.

[Daniel Sanders]

I've got a few comments but nothing major. LGTM with those.


================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:90
@@ -90,1 +89,3 @@
+      Mips::FeatureFP64Bit | Mips::FeatureGP64Bit | Mips::FeatureNaN2008 |
+      Mips::FeatureSoftFloat;
 
----------------
I don't think soft-float is an arch related feature. Does '.set mips32' and similar reset it?

================
Comment at: lib/Target/Mips/Mips32r6InstrInfo.td:655
@@ +654,3 @@
+def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6,
+             AdditionalRequires<[IsNotSoftFloat]>;
+def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6,
----------------
We should extend PredicateControl with a SoftFloatPredicates member and add adjectives (HARDFLOAT/SOFTFLOAT?) to set that.

================
Comment at: lib/Target/Mips/MipsInstrFPU.td:120
@@ -112,3 +119,3 @@
   def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
-             AdditionalRequires<[NotFP64bit]>;
+             AdditionalRequires<[NotFP64bit, IsNotSoftFloat]>;
   def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
----------------
This isn't related to your patch so no change required in this patch: NotFP64bit and IsFP64bit belong in PredicateControl.FGRPredicates, not in PredicateControl.AdditionalPredicates. The FGR_64 and FGR_32 adjectives can be used to do this.

There seems to be a few instances of this kind of thing left.

================
Comment at: lib/Target/Mips/MipsInstrFPU.td:408-409
@@ -394,3 +407,4 @@
 
-let DecoderNamespace = "Mips64" in {
+let DecoderNamespace = "Mips64"
+in {
   def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2,
----------------
Nit: Why break the line?

================
Comment at: lib/Target/Mips/MipsInstrFPU.td:438
@@ -423,2 +437,3 @@
 
+// Does this work with +soft-float ??
 let DecoderNamespace="Mips64" in {
----------------
> Does this work with +soft-float ??
They require hardfloat.

http://reviews.llvm.org/D9053

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