[PATCH] [mips] [IAS] Inline assemble-time shifting out of createLShiftOri. NFC.

[Daniel Sanders]

================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:1735
@@ -1735,1 +1734,3 @@
     //           ori d,d,lo16(j)
+    uint16_t Hi16 = (ImmValue & (0xffffLL << 16)) >> 16;
+    uint16_t Lo16 = ImmValue & 0xffffLL;
----------------
Why not this?
  (ImmValue >> 16) & 0xffff
Likewise for the others.

================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:1762
@@ -1759,1 +1761,3 @@
     //           ori d,d,lo16(lo32(j))
+    uint16_t Lo16OfHi32 = (ImmValue & (0xffffLL << 32)) >> 32;
+    uint16_t Hi16OfLo32 = (ImmValue & (0xffffLL << 16)) >> 16;
----------------
Optional: Consider names of the form Bits47To32

http://reviews.llvm.org/D8973

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