[llvm] r234593 - [AArch64] Adjusts Cortex-A57 machine model to handle zero shift.

[Chad Rosier]

Author: mcrosier
Date: Fri Apr 10 08:19:21 2015
New Revision: 234593

URL: http://llvm.org/viewvc/llvm-project?rev=234593&view=rev
Log:
[AArch64] Adjusts Cortex-A57 machine model to handle zero shift.

http://reviews.llvm.org/D8043
Patch by Dave Estes <cestes at codeaurora.org>!

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td?rev=234593&r1=234592&r2=234593&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td Fri Apr 10 08:19:21 2015
@@ -127,6 +127,15 @@ def : InstRW<[A57Write_1cyc_1B_1I], (ins
 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
 
 
+// Shifted Register with Shift == 0
+// ----------------------------------------------------------------------------
+
+def A57WriteISReg : SchedWriteVariant<[
+       SchedVar<RegShiftedPred, [WriteISReg]>,
+       SchedVar<NoSchedPred, [WriteI]>]>;
+def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
+
+
 // Divide and Multiply Instructions
 // -----------------------------------------------------------------------------