[PATCH] [AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.

[Ana Pazos]

I have verified that with this patch the MachineCombiner pass works better and we are able to generate more multiply-add instructions on a57. Before we were missing opportunities due to wrong computation of forwarding latency (e.g., mul instruction that feeds into a madd instruction as its accumulator should have a reduced latency).


http://reviews.llvm.org/D8045

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