[llvm] r233986 - MachineRegisterInfo: Make it clear that hints are for vregs

Quentin Colombet qcolombet at apple.com
Fri Apr 3 10:23:23 PDT 2015


Fair enough!

Just saw your ARM fix, and yeah that would have helped then :).

Q.
> On Apr 3, 2015, at 10:13 AM, Matthias Braun <matze at braunis.de> wrote:
> 
> Simply because I spent 10 minutes thinking about it and thought I can safe the next person that time.
> 
> - Matthias
> 
>> On Apr 3, 2015, at 10:02 AM, Quentin Colombet <qcolombet at apple.com> wrote:
>> 
>> Hi Matthias,
>> 
>> Although your change is correct, why do you need to make it clear?
>> 
>> Setting hint for physical register won’t change their allocation :).
>> 
>> Cheers,
>> -Quentin
>> 
>>> On Apr 2, 2015, at 5:18 PM, Matthias Braun <matze at braunis.de> wrote:
>>> 
>>> Author: matze
>>> Date: Thu Apr  2 19:18:33 2015
>>> New Revision: 233986
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=233986&view=rev
>>> Log:
>>> MachineRegisterInfo: Make it clear that hints are for vregs
>>> 
>>> Modified:
>>>  llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
>>> 
>>> Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=233986&r1=233985&r2=233986&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)
>>> +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Thu Apr  2 19:18:33 2015
>>> @@ -620,22 +620,25 @@ public:
>>> 
>>> /// setRegAllocationHint - Specify a register allocation hint for the
>>> /// specified virtual register.
>>> -  void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
>>> -    RegAllocHints[Reg].first  = Type;
>>> -    RegAllocHints[Reg].second = PrefReg;
>>> +  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
>>> +    assert(TargetRegisterInfo::isVirtualRegister(VReg));
>>> +    RegAllocHints[VReg].first  = Type;
>>> +    RegAllocHints[VReg].second = PrefReg;
>>> }
>>> 
>>> /// getRegAllocationHint - Return the register allocation hint for the
>>> /// specified virtual register.
>>> std::pair<unsigned, unsigned>
>>> -  getRegAllocationHint(unsigned Reg) const {
>>> -    return RegAllocHints[Reg];
>>> +  getRegAllocationHint(unsigned VReg) const {
>>> +    assert(TargetRegisterInfo::isVirtualRegister(VReg));
>>> +    return RegAllocHints[VReg];
>>> }
>>> 
>>> /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
>>> /// standard simple hint (Type == 0) is not set.
>>> -  unsigned getSimpleHint(unsigned Reg) const {
>>> -    std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
>>> +  unsigned getSimpleHint(unsigned VReg) const {
>>> +    assert(TargetRegisterInfo::isVirtualRegister(VReg));
>>> +    std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
>>>   return Hint.first ? 0 : Hint.second;
>>> }
>>> 
>>> 
>>> 
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>> 
>> 
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