[llvm] r233635 - Transfer implicit operands when expanding the RET_ReallyLR pseudo instruction.

[Juergen Ributzka]

Author: ributzka
Date: Mon Mar 30 17:45:56 2015
New Revision: 233635

URL: http://llvm.org/viewvc/llvm-project?rev=233635&view=rev
Log:
Transfer implicit operands when expanding the RET_ReallyLR pseudo instruction.

When we expand the RET_ReallyLR pseudo instruction we also need to transfer the
implicit operands.

The return register is an implicit operand and without it the liveness
calculation generates an incorrect live-out set for the patchpoint.

This fixes rdar://problem/19068476.

Added:
    llvm/trunk/test/CodeGen/AArch64/stackmap-liveness.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp?rev=233635&r1=233634&r2=233635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp Mon Mar 30 17:45:56 2015
@@ -698,12 +698,15 @@ bool AArch64ExpandPseudo::expandMI(Machi
     return expandMOVImm(MBB, MBBI, 32);
   case AArch64::MOVi64imm:
     return expandMOVImm(MBB, MBBI, 64);
-  case AArch64::RET_ReallyLR:
-    BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
-        .addReg(AArch64::LR);
+  case AArch64::RET_ReallyLR: {
+    MachineInstrBuilder MIB =
+        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
+          .addReg(AArch64::LR);
+    transferImpOps(MI, MIB, MIB);
     MI.eraseFromParent();
     return true;
   }
+  }
   return false;
 }
 

Added: llvm/trunk/test/CodeGen/AArch64/stackmap-liveness.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/stackmap-liveness.ll?rev=233635&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/stackmap-liveness.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/stackmap-liveness.ll Mon Mar 30 17:45:56 2015
@@ -0,0 +1,47 @@
+; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+; CHECK-LABEL:  .section  __LLVM_STACKMAPS,__llvm_stackmaps
+; CHECK-NEXT:   __LLVM_StackMaps:
+; Header
+; CHECK-NEXT:   .byte 1
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .short 0
+; Num Functions
+; CHECK-NEXT:   .long 1
+; Num LargeConstants
+; CHECK-NEXT:   .long   0
+; Num Callsites
+; CHECK-NEXT:   .long   1
+
+; Functions and stack size
+; CHECK-NEXT:   .quad _stackmap_liveness
+; CHECK-NEXT:   .quad 16
+
+; Test that the return register is recognized as an live-out.
+define i64 @stackmap_liveness(i1 %c) {
+; CHECK-LABEL:  .long L{{.*}}-_stackmap_liveness
+; CHECK-NEXT:   .short  0
+; CHECK-NEXT:   .short  0
+; Padding
+; CHECK-NEXT:   .short  0
+; Num LiveOut Entries: 1
+; CHECK-NEXT:   .short  2
+; LiveOut Entry 0: X0
+; CHECK-NEXT:   .short 0
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .byte 8
+; LiveOut Entry 1: SP
+; CHECK-NEXT:   .short 31
+; CHECK-NEXT:   .byte 0
+; CHECK-NEXT:   .byte 8
+; Align
+; CHECK-NEXT:   .align  3
+  %1 = select i1 %c, i64 1, i64 2
+  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 32, i8* null, i32 0)
+  ret i64 %1
+}
+
+declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
+