[PATCH] [PPC64LE] Remove unnecessary swaps from lane-insensitive vector computations

[Bill Schmidt]

Eric and I had a short chat about the option situation on IRC.  Apparently there really isn't a good mechanism for disabling a specific pass for a specific target right now.  I am fine with removing the option portion of this for now until LLVM supports a proper way of doing this.  The down side is losing the chicken switch of a quick workaround.  Since this is a -O1 optimization, the workaround becomes -O0 (or -O0 -no-fast-isel) which is somewhat harsh.

Responses to inline comments ... inline!


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Comment at: lib/Target/PowerPC/PPCVSXSwapRemoval.cpp:204
@@ +203,3 @@
+
+  const int InitialVectorSize(256);
+  SwapVector.clear();
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echristo wrote:
> 256?
Hey, a magic constant.  That's why I gave it a name. :)  Picking an initial vector size to avoid too many reallocations while keeping the size reasonable.  Yes, it's a wet thumb to the breeze...

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Comment at: lib/Target/PowerPC/PPCVSXSwapRemoval.cpp:251
@@ +250,3 @@
+      switch(MI->getOpcode()) {
+      default:
+        // Unless noted otherwise, an instruction is considered
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echristo wrote:
> What instructions not listed are you thinking here?
A vast number of lane-insensitive instructions.  All of the vector math, logical, select, etc.  Everything that's true SIMD.

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Comment at: lib/Target/PowerPC/PPCVSXSwapRemoval.cpp:614
@@ +613,3 @@
+
+        for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
+          int UseIdx = SwapMap[&UseMI];
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echristo wrote:
> Good point, what _does_ this do for debug info? :)
It doesn't do anything, but it doesn't need to.  When the load or store is initially expanded, its location information goes on the LXVD2X and XXPERMDI instructions, or on the XXPERMDI and STXVD2X instructions.  This pass removes the XXPERMDI instructions, but the location information remains with the LXVD2X or STXVD2X.

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Comment at: lib/Target/PowerPC/PPCVSXSwapRemoval.cpp:646
@@ +645,3 @@
+// here.
+void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
+}
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echristo wrote:
> ?
As noted in the overall patch commentary, there are non-pure-SIMD instructions for which we can still perform this optimization, provided we change code generation for those instructions.  My plan is to fill in this function with the details in future patches.  The initial patch is for the "simple" part (which covers a great many cases).

http://reviews.llvm.org/D8565

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