# [RFC][PATCH][LoopVectorize] Teach Loop Vectorizer about interleaved data accesses

Hao Liu Hao.Liu at arm.com
Fri Mar 20 04:47:52 PDT 2015

```Hi,

There are two patches attached can achieve this goal:

interleaved data access and generate target independent intrinsics for each

AArch64Backend-MatchIntrinsics.patch match several target independent
intrinsics into one AArch64 ldN/stN intrinsics, so that AArch64 backend can
generate ldN/stN instructions.

Currently, LoopVectorize can vectorize consecutive accesses well. It can
vectorize loops like

for (int i = 0; i < n; i++)

sum += R[i];

But it doesn't handle strided access well. Interleaved access is a subset of
strided access. Example for interleaved access:

for (int i = 0; i < n; i++) {

int even = A[2*i];

int odd = A[2*i + 1];

// do something with odd & even.

}

To vectorize such case, we need two vectors: one with even elements, another
with odd elements. To gather even elements, we need several scalar loads for
"A[0], A[2], A[4], ...", and several INSERT_ELEMENTs to combine them
together. The cost is very high and will usually prevent loop vectorization
on such case. Some backend like AArch64/ARM support interleaved load/store:
ldN/stN (N is 2/3/4). And I know X86 can also support similar operations.
One ld2 can load two vectors: one is with even elements, another is with
only odd elements. So that this case can be vectorized into AArch64
instructions:

LD2 { V0, V1 } [X0]

// V0 contains even elements. Do something related to even elements
with V0.

// V1 contains odd elements. Do something related to odd elements with
V1.

1. Design

My design is to follow current Loop Vecotirzer three phases.

(1) Legality Phase:

(a). Collect all the constant strided accesses except consecutive
accesses.

(b). Collect the load/store accesses with the same Stride, Base pointer.

(c). Fine the consecutive chains in (b). If the number of accesses in
one chain are equal to the Stride, they are interleaved accesses.

Example for the case about even and odd. We can find two loads for even and
odd elements. The strides are both 2. They are also consecutive. So they are
recorded as interleaved accesses.

(2) Profitability Phase:

Add a target hook to calculate the cost. Currently the cost is 1.
Currently this won't affect to much about the result. So I didn't do too
much work in this phase.

(3) Transform Phase:

As there is no IR for interleaved data, I think we should use
intrinsics. The problem is that the relationship is "N to one". I.E. Several
intrinsics in AArch64/ARM backend such llvm.aarch64.neon.ldN, which is like
"call { <4 x i32>, <4 x i32>} llvm.aarch64.neon.ld2.v4i32()". In the middle
end, there are two IR loads.

Need to think a way to match two loads to one target specific intrinsic. I
think there are two ways:

(a). Two steps for middle end and backend. 1st step is to match each
loads/stores to one target independent intrinsic in the loop vectorize. 2nd
step is to match several intrinsics into one ldN/stN intrinsic. This is the
choise of my attached patch. For the above odd-even example, it will
generate two intrinsics in the loop vectorization:

"%even-elements = call <4 x i32>

"%odd-elements = call <4 x i32>

A backend pass will combine them together into one intrinsic:

"%even-odd-elements = call { <4 x i32>, <4 x i32> }
@llvm.aarch64.neon.ld2.v4i32"

But I think the backend pass is vulnerable and diffecult to implement. It
will fail to combine if one load is missing, or if one load is moved to
another basic block. Also I haven't check about memory dependency.

(b). One step only for middle end. We can match several load/stores
into one ldN/stN like target independent intrinsic. So that the AArch64/ARM
backend only needs slight modification on replacing the current used
intrinsic to the new independent intrinsic. This needs to introduce a new
intrinsic such as "{ <4 x i32>, <4 x i32>} llvm.interleaved.load.v4i32()".

Actually I prefer solution (b), which is easier to be implemented and
stronger than solution (a). But solution (a) seems more target independent.
How do you guys think?

2. Test

I've test the attached patch with llvm-test-suit, SPEC2000, SPEC2006, EEMBC,
Geekbench on AArch64 machine. They all can pass.

But the performance is not affected. Some specific benchmarks like EEMBC
rgbcmy and EEMBC rgbyiq are expected to have several times of acceleration.
The reason is that there are other issues prevent vectorization
opportunities. Some known issues are:

(1). Too many unnecessary runtime checkings (The interleaved accesses
are compared with each other).

accesses).

(3). Type promotion issue (i8 is illegal but <16 x i8> is legal. i8 is
promoted to i32 so the extend and truncate operations increase the total
cost).

(4). The Vector Factor is selected according to the widest type. (If
there are both i8 and i32, we select a small factor according to i32 rather
than according to i8).

Anyway. We can fix them in the future and get performance improvements.

transform phase.

Thanks,

-Hao
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