[PATCH] [X86, AVX] use blends instead of insert128 with index 0

Andrea Di Biagio Andrea_DiBiagio at sn.scee.net
Thu Mar 19 14:52:48 PDT 2015

Comment at: test/CodeGen/X86/avx-cast.ll:9-12
@@ -6,1 +8,6 @@
 define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp {
+; AVX1-LABEL: castA:
+; AVX1:         vxorps %ymm1, %ymm1, %ymm1
+; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
+; AVX1-NEXT:    retq
spatel wrote:
> andreadb wrote:
> > Would it be possible to also have a test where the vector insertion is not performed on a zero vector? Apparently all the test cases you modified only seem to test the case case where a vector is inserted in the low 128-bit lane of a zero vector.
> Let me make sure I understand the scenario. Is it different that this:
>   define <4 x double> @shuffle_v4f64_0167(<4 x double> %a, <4 x double> %b) {
>   ; ALL-LABEL: shuffle_v4f64_0167:
>   ; ALL:       # BB#0:
>   ; ALL-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
>   ; ALL-NEXT:    retq
>     %shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
>     ret <4 x double> %shuffle
>   }
> I think the existing shuffle lowering was already detecting the non-zero version, so there are existing test cases that cover it (the above is in vector-shuffle-256-v4.ll). Please let me know if I've misunderstood.
That matches what I originally thought: the non-zero cases are handled by other parts of the shuffle lowering logic.
I just wanted to make sure that we had a good test coverage :-).
I think your patch is OK. Thanks!



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