[llvm] r231259 - R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32

[Tom Stellard]

On Mon, Mar 16, 2015 at 11:39:30PM +0100, Marek Olšák wrote:
> Hi Tom,
> 
> Can this commit be cherry-picked to stable? We'll need it for the GL4
> extension and it would be nice to get it sooner than later.
> 

Sure, no problem.

-Tom

> Thanks,
> 
> Marek
> 
> On Wed, Mar 4, 2015 at 6:33 PM, Marek Olsak <marek.olsak at amd.com> wrote:
> > Author: mareko
> > Date: Wed Mar  4 11:33:45 2015
> > New Revision: 231259
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=231259&view=rev
> > Log:
> > R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32
> >
> > Required by OpenGL (ARB_gpu_shader5).
> >
> > Added:
> >     llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll
> > Modified:
> >     llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td
> >     llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
> >     llvm/trunk/lib/Target/R600/SIInstructions.td
> >
> > Modified: llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td?rev=231259&r1=231258&r2=231259&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td (original)
> > +++ llvm/trunk/lib/Target/R600/AMDGPUIntrinsics.td Wed Mar  4 11:33:45 2015
> > @@ -68,6 +68,7 @@ let TargetPrefix = "AMDGPU", isTarget =
> >    def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> >    def int_AMDGPU_bfm : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
> >    def int_AMDGPU_brev : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
> > +  def int_AMDGPU_flbit_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
> >    def int_AMDGPU_barrier_local  : Intrinsic<[], [], []>;
> >    def int_AMDGPU_barrier_global  : Intrinsic<[], [], []>;
> >  }
> >
> > Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=231259&r1=231258&r2=231259&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)
> > +++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Wed Mar  4 11:33:45 2015
> > @@ -1420,6 +1420,7 @@ unsigned SIInstrInfo::getVALUOp(const Ma
> >    case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
> >    case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
> >    case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
> > +  case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
> >    }
> >  }
> >
> >
> > Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=231259&r1=231258&r2=231259&view=diff
> > ==============================================================================
> > --- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
> > +++ llvm/trunk/lib/Target/R600/SIInstructions.td Wed Mar  4 11:33:45 2015
> > @@ -153,7 +153,9 @@ defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x1
> >  >;
> >
> >  defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>;
> > -defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32", []>;
> > +defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32",
> > +  [(set i32:$dst, (int_AMDGPU_flbit_i32 i32:$src0))]
> > +>;
> >  defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>;
> >  defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8",
> >    [(set i32:$dst, (sext_inreg i32:$src0, i8))]
> >
> > Added: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll?rev=231259&view=auto
> > ==============================================================================
> > --- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll (added)
> > +++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll Wed Mar  4 11:33:45 2015
> > @@ -0,0 +1,28 @@
> > +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> > +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> > +
> > +declare i32 @llvm.AMDGPU.flbit.i32(i32) nounwind readnone
> > +
> > +; FUNC-LABEL: {{^}}s_flbit:
> > +; SI: s_load_dword [[VAL:s[0-9]+]],
> > +; SI: s_flbit_i32 [[SRESULT:s[0-9]+]], [[VAL]]
> > +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
> > +; SI: buffer_store_dword [[VRESULT]],
> > +; SI: s_endpgm
> > +define void @s_flbit(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
> > +  %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone
> > +  store i32 %r, i32 addrspace(1)* %out, align 4
> > +  ret void
> > +}
> > +
> > +; FUNC-LABEL: {{^}}v_flbit:
> > +; SI: buffer_load_dword [[VAL:v[0-9]+]],
> > +; SI: v_ffbh_i32_e32 [[RESULT:v[0-9]+]], [[VAL]]
> > +; SI: buffer_store_dword [[RESULT]],
> > +; SI: s_endpgm
> > +define void @v_flbit(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
> > +  %val = load i32, i32 addrspace(1)* %valptr, align 4
> > +  %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone
> > +  store i32 %r, i32 addrspace(1)* %out, align 4
> > +  ret void
> > +}
> >
> >
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