[PATCH] Do not use isel on P7 and P8

hfinkel at anl.gov hfinkel at anl.gov
Mon Mar 16 23:08:26 PDT 2015

> ifcvt.ll: using A2 does not generate isel (Hal: seems fishy, right?)

Yea, we should figure this out.

> p8-isel-sched.ll: shall we remove this testcase?

No, but once you control this using some target feature, you can enable it specifically for this test.

Also, one more wrinkle, we should still generate isel on the p7/p8 when optimizing for size.

Comment at: lib/Target/PowerPC/PPCSubtarget.h:268
@@ +267,3 @@
+  // non-trivial latency for those subtargets.
+  bool useISELRatherThanBranches() const {
+    return HasISEL &&
I don't want to do it this way. Either just remove HasISEL from the `P7`/`P8` processor definitions, or add a ISELIsSlow (or whatever) to PPC.td, but we shouldn't hard code it like this here.

Comment at: test/CodeGen/PowerPC/crbit-asm.ll:1
@@ -1,2 +1,2 @@
 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
Please keep the isel test coverage here (and in crbit.ll below), but we can use different -check-prefix when running on the pwr7 vs. the a2.



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