[PATCH] Fix R0 use in PowerPC VSX store for FastIsel

Samuel Antao sfantao at us.ibm.com
Mon Mar 16 11:19:21 PDT 2015

Before this fix, there were instructions being generated like this:

STXSDX %http://reviews.llvm.org/F1<kill>, %X3<kill>, %noreg, %RM<imp-use>

The code seems be prepared to handle %noreg. R0 was being emitted for %noreg. The problem here is not the register class but the order of the operands. If FastISel were emitting something like:

STXSDX %http://reviews.llvm.org/F1<kill>, %X3<kill>, %ZERO8, %RM<imp-use>

we would still have a problem, as the content of R0 would be taken to compute the effective address of the store. If we have:

STXSDX %http://reviews.llvm.org/F1<kill>, %ZERO8, %X3<kill>, %RM<imp-use>

this works fine as R0 used as based address makes 0 to be used in the computation of the effective address instead of the value contained in R0. We are doing something similar for when UseOffset is set, the immediate has to come before the base register in order to get the right semantics.




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